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e2e2fc3cd0
Add updated patches for 6.6. DMA/cache-handling patches have been reworked / backported from upstream. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
161 lines
4.6 KiB
Diff
161 lines
4.6 KiB
Diff
From 8e090d271683d5869cdab0729f54a8af8c79c476 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Tue, 31 Oct 2023 15:14:44 +0100
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Subject: [PATCH 1016/1024] soc: sifive: ccache: Add StarFive JH7100 support
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This adds support for the StarFive JH7100 SoC which also features this
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SiFive cache controller.
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The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom
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exension, so instead we need to use this cache controller for
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non-standard cache management operations.
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Unfortunately the interrupt for uncorrected data is broken on the JH7100
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and fires continuously, so add a quirk to not register a handler for it.
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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---
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drivers/soc/sifive/sifive_ccache.c | 62 +++++++++++++++++++++++++++++-
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1 file changed, 60 insertions(+), 2 deletions(-)
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--- a/drivers/soc/sifive/sifive_ccache.c
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+++ b/drivers/soc/sifive/sifive_ccache.c
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@@ -8,13 +8,16 @@
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#define pr_fmt(fmt) "CCACHE: " fmt
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+#include <linux/align.h>
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#include <linux/debugfs.h>
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#include <linux/interrupt.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/device.h>
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#include <linux/bitfield.h>
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+#include <asm/cacheflush.h>
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#include <asm/cacheinfo.h>
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+#include <asm/dma-noncoherent.h>
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#include <soc/sifive/sifive_ccache.h>
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#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
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@@ -39,10 +42,14 @@
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#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16)
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#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24)
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+#define SIFIVE_CCACHE_FLUSH64 0x200
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+#define SIFIVE_CCACHE_FLUSH32 0x240
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+
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#define SIFIVE_CCACHE_WAYENABLE 0x08
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#define SIFIVE_CCACHE_ECCINJECTERR 0x40
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#define SIFIVE_CCACHE_MAX_ECCINTR 4
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+#define SIFIVE_CCACHE_LINE_SIZE 64
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static void __iomem *ccache_base;
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static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
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@@ -56,6 +63,11 @@ enum {
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DIR_UNCORR,
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};
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+enum {
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+ QUIRK_NONSTANDARD_CACHE_OPS = BIT(0),
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+ QUIRK_BROKEN_DATA_UNCORR = BIT(1),
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+};
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+
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#ifdef CONFIG_DEBUG_FS
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static struct dentry *sifive_test;
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@@ -106,6 +118,8 @@ static void ccache_config_read(void)
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static const struct of_device_id sifive_ccache_ids[] = {
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{ .compatible = "sifive,fu540-c000-ccache" },
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{ .compatible = "sifive,fu740-c000-ccache" },
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+ { .compatible = "starfive,jh7100-ccache",
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+ .data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS | QUIRK_BROKEN_DATA_UNCORR) },
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{ .compatible = "sifive,ccache0" },
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{ /* end of table */ }
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};
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@@ -124,6 +138,34 @@ int unregister_sifive_ccache_error_notif
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}
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EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier);
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+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
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+static void ccache_flush_range(phys_addr_t start, size_t len)
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+{
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+ phys_addr_t end = start + len;
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+ phys_addr_t line;
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+
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+ if (!len)
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+ return;
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+
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+ mb();
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+ for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end;
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+ line += SIFIVE_CCACHE_LINE_SIZE) {
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+#ifdef CONFIG_32BIT
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+ writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32);
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+#else
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+ writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64);
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+#endif
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+ mb();
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+ }
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+}
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+
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+static const struct riscv_nonstd_cache_ops ccache_mgmt_ops __initconst = {
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+ .wback = &ccache_flush_range,
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+ .inv = &ccache_flush_range,
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+ .wback_inv = &ccache_flush_range,
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+};
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+#endif /* CONFIG_RISCV_NONSTANDARD_CACHE_OPS */
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+
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static int ccache_largest_wayenabled(void)
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{
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return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF;
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@@ -210,11 +252,15 @@ static int __init sifive_ccache_init(voi
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struct device_node *np;
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struct resource res;
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int i, rc, intr_num;
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+ const struct of_device_id *match;
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+ unsigned long quirks;
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- np = of_find_matching_node(NULL, sifive_ccache_ids);
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+ np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &match);
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if (!np)
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return -ENODEV;
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+ quirks = (uintptr_t)match->data;
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+
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if (of_address_to_resource(np, 0, &res)) {
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rc = -ENODEV;
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goto err_node_put;
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@@ -240,6 +286,10 @@ static int __init sifive_ccache_init(voi
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for (i = 0; i < intr_num; i++) {
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g_irq[i] = irq_of_parse_and_map(np, i);
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+
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+ if (i == DATA_UNCORR && (quirks & QUIRK_BROKEN_DATA_UNCORR))
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+ continue;
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+
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rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc",
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NULL);
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if (rc) {
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@@ -249,6 +299,14 @@ static int __init sifive_ccache_init(voi
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}
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of_node_put(np);
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+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
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+ if (quirks & QUIRK_NONSTANDARD_CACHE_OPS) {
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+ riscv_cbom_block_size = SIFIVE_CCACHE_LINE_SIZE;
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+ riscv_noncoherent_supported();
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+ riscv_noncoherent_register_cache_ops(&ccache_mgmt_ops);
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+ }
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+#endif
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+
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ccache_config_read();
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ccache_cache_ops.get_priv_group = ccache_get_priv_group;
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@@ -269,4 +327,4 @@ err_node_put:
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return rc;
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}
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-device_initcall(sifive_ccache_init);
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+arch_initcall(sifive_ccache_init);
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