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28f534d953
Update patch set for new release and add required kernel option CONFIG_ZRAM_TRACK_ENTRY_ACTIME to generic config Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.66 Manually rebased: bcm27xx/patches-6.6/950-0092-MMC-added-alternative-MMC-driver.patch bcm53xx/patches-6.6/180-usb-xhci-add-support-for-performing-fake-doorbell.patch starfive/patches-6.6/1000-serial-8250_dw-Add-starfive-jh7100-hsuart-compatible.patch Removed upstreamed: bcm27xx/patches-6.6/950-0029-vc4_hdmi-Avoid-log-spam-for-audio-start-failure.patch[1] All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.66&id=e0388a95736abd1f5f5a94221dd1ac24eacbd4d7 Build system: x86/64 Build-tested: bcm27xx/bcm2712, flogic/glinet_gl-mt6000, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3, x86/64 Run-tested: bcm27xx/bcm2712, flogic/glinet_gl-mt6000, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3, x86/64 Signed-off-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/17271 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
246 lines
9.2 KiB
Diff
246 lines
9.2 KiB
Diff
From 69cb89981c7a181d857b634c0740e914d5df79ea Mon Sep 17 00:00:00 2001
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From: ChunHao Lin <hau@realtek.com>
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Date: Fri, 30 Aug 2024 10:18:10 +0800
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Subject: [PATCH] r8169: add support for RTL8126A rev.b
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Add support for RTL8126A rev.b. Its XID is 0x64a. It is basically
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based on the one with XID 0x649, but with different firmware file.
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Signed-off-by: ChunHao Lin <hau@realtek.com>
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Reviewed-by: Heiner Kallweit <hkallweit1@gmail.com>
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Link: https://patch.msgid.link/20240830021810.11993-1-hau@realtek.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/ethernet/realtek/r8169.h | 1 +
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drivers/net/ethernet/realtek/r8169_main.c | 42 ++++++++++++-------
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.../net/ethernet/realtek/r8169_phy_config.c | 1 +
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3 files changed, 29 insertions(+), 15 deletions(-)
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--- a/drivers/net/ethernet/realtek/r8169.h
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+++ b/drivers/net/ethernet/realtek/r8169.h
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@@ -69,6 +69,7 @@ enum mac_version {
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RTL_GIGA_MAC_VER_61,
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RTL_GIGA_MAC_VER_63,
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RTL_GIGA_MAC_VER_65,
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+ RTL_GIGA_MAC_VER_66,
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RTL_GIGA_MAC_NONE
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};
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--- a/drivers/net/ethernet/realtek/r8169_main.c
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+++ b/drivers/net/ethernet/realtek/r8169_main.c
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@@ -56,6 +56,7 @@
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#define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
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#define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"
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#define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw"
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+#define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw"
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#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
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#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
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@@ -138,6 +139,7 @@ static const struct {
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/* reserve 62 for CFG_METHOD_4 in the vendor driver */
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[RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2},
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[RTL_GIGA_MAC_VER_65] = {"RTL8126A", FIRMWARE_8126A_2},
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+ [RTL_GIGA_MAC_VER_66] = {"RTL8126A", FIRMWARE_8126A_3},
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};
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static const struct pci_device_id rtl8169_pci_tbl[] = {
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@@ -1228,7 +1230,7 @@ static void rtl_writephy(struct rtl8169_
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case RTL_GIGA_MAC_VER_31:
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r8168dp_2_mdio_write(tp, location, val);
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break;
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- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
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+ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:
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r8168g_mdio_write(tp, location, val);
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break;
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default:
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@@ -1243,7 +1245,7 @@ static int rtl_readphy(struct rtl8169_pr
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case RTL_GIGA_MAC_VER_28:
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case RTL_GIGA_MAC_VER_31:
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return r8168dp_2_mdio_read(tp, location);
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- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
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+ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:
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return r8168g_mdio_read(tp, location);
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default:
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return r8169_mdio_read(tp, location);
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@@ -1452,7 +1454,7 @@ static void rtl_set_d3_pll_down(struct r
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case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
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case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
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case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
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- case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65:
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+ case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_66:
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if (enable)
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RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
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else
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@@ -1619,7 +1621,7 @@ static void __rtl8169_set_wol(struct rtl
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break;
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case RTL_GIGA_MAC_VER_34:
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case RTL_GIGA_MAC_VER_37:
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- case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65:
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+ case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_66:
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if (wolopts)
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rtl_mod_config2(tp, 0, PME_SIGNAL);
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else
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@@ -2098,6 +2100,7 @@ static void rtl_set_eee_txidle_timer(str
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case RTL_GIGA_MAC_VER_61:
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case RTL_GIGA_MAC_VER_63:
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case RTL_GIGA_MAC_VER_65:
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+ case RTL_GIGA_MAC_VER_66:
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tp->tx_lpi_timer = timer_val;
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RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val);
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break;
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@@ -2227,6 +2230,7 @@ static enum mac_version rtl8169_get_mac_
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enum mac_version ver;
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} mac_info[] = {
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/* 8126A family. */
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+ { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_66 },
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{ 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 },
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/* 8125B family. */
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@@ -2498,6 +2502,7 @@ static void rtl_init_rxcfg(struct rtl816
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break;
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case RTL_GIGA_MAC_VER_63:
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case RTL_GIGA_MAC_VER_65:
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+ case RTL_GIGA_MAC_VER_66:
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RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
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RX_PAUSE_SLOT_ON);
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break;
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@@ -2684,7 +2689,7 @@ static void rtl_wait_txrx_fifo_empty(str
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case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
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rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
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break;
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- case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_65:
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+ case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66:
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RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
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rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
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rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
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@@ -2927,7 +2932,7 @@ static void rtl_enable_exit_l1(struct rt
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case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
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rtl_eri_set_bits(tp, 0xd4, 0x0c00);
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break;
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- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
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+ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:
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r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
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break;
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default:
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@@ -2941,7 +2946,7 @@ static void rtl_disable_exit_l1(struct r
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case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
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rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
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break;
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- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
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+ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:
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r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
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break;
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default:
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@@ -2968,6 +2973,7 @@ static void rtl_hw_aspm_clkreq_enable(st
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rtl_mod_config5(tp, 0, ASPM_en);
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switch (tp->mac_version) {
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case RTL_GIGA_MAC_VER_65:
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+ case RTL_GIGA_MAC_VER_66:
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val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN;
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RTL_W8(tp, INT_CFG0_8125, val8);
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break;
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@@ -2978,7 +2984,7 @@ static void rtl_hw_aspm_clkreq_enable(st
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switch (tp->mac_version) {
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case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
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- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
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+ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:
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/* reset ephy tx/rx disable timer */
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r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
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/* chip can trigger L1.2 */
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@@ -2990,7 +2996,7 @@ static void rtl_hw_aspm_clkreq_enable(st
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} else {
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switch (tp->mac_version) {
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case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
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- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
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+ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:
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r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
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break;
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default:
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@@ -2999,6 +3005,7 @@ static void rtl_hw_aspm_clkreq_enable(st
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switch (tp->mac_version) {
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case RTL_GIGA_MAC_VER_65:
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+ case RTL_GIGA_MAC_VER_66:
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val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN;
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RTL_W8(tp, INT_CFG0_8125, val8);
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break;
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@@ -3718,10 +3725,12 @@ static void rtl_hw_start_8125_common(str
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/* disable new tx descriptor format */
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r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
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- if (tp->mac_version == RTL_GIGA_MAC_VER_65)
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+ if (tp->mac_version == RTL_GIGA_MAC_VER_65 ||
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+ tp->mac_version == RTL_GIGA_MAC_VER_66)
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RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02);
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- if (tp->mac_version == RTL_GIGA_MAC_VER_65)
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+ if (tp->mac_version == RTL_GIGA_MAC_VER_65 ||
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+ tp->mac_version == RTL_GIGA_MAC_VER_66)
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r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
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else if (tp->mac_version == RTL_GIGA_MAC_VER_63)
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r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
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@@ -3739,7 +3748,8 @@ static void rtl_hw_start_8125_common(str
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r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
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r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
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r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
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- if (tp->mac_version == RTL_GIGA_MAC_VER_65)
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+ if (tp->mac_version == RTL_GIGA_MAC_VER_65 ||
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+ tp->mac_version == RTL_GIGA_MAC_VER_66)
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r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000);
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else
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r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
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@@ -3853,6 +3863,7 @@ static void rtl_hw_config(struct rtl8169
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[RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
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[RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
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[RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a,
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+ [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8126a,
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};
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if (hw_configs[tp->mac_version])
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@@ -3873,6 +3884,7 @@ static void rtl_hw_start_8125(struct rtl
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break;
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case RTL_GIGA_MAC_VER_63:
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case RTL_GIGA_MAC_VER_65:
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+ case RTL_GIGA_MAC_VER_66:
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for (i = 0xa00; i < 0xa80; i += 4)
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RTL_W32(tp, i, 0);
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RTL_W16(tp, INT_CFG1_8125, 0x0000);
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@@ -4101,7 +4113,7 @@ static void rtl8169_cleanup(struct rtl81
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RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
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rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
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break;
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- case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65:
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+ case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:
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rtl_enable_rxdvgate(tp);
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fsleep(2000);
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break;
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@@ -4258,7 +4270,7 @@ static unsigned int rtl_quirk_packet_pad
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switch (tp->mac_version) {
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case RTL_GIGA_MAC_VER_34:
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- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
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+ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:
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padto = max_t(unsigned int, padto, ETH_ZLEN);
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break;
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default:
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@@ -5294,7 +5306,7 @@ static void rtl_hw_initialize(struct rtl
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case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
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rtl_hw_init_8168g(tp);
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break;
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- case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65:
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+ case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:
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rtl_hw_init_8125(tp);
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break;
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default:
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--- a/drivers/net/ethernet/realtek/r8169_phy_config.c
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+++ b/drivers/net/ethernet/realtek/r8169_phy_config.c
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@@ -1161,6 +1161,7 @@ void r8169_hw_phy_config(struct rtl8169_
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[RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config,
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[RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config,
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[RTL_GIGA_MAC_VER_65] = rtl8126a_hw_phy_config,
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+ [RTL_GIGA_MAC_VER_66] = rtl8126a_hw_phy_config,
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};
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if (phy_configs[ver])
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