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9131cb44ff
Introduce EN7581 SoC support with currently rfb board supported. This is a new 64bit SoC from Airoha that is currently almost fully supported upstream with only the DTS missing. Setting source-only waiting for the full upstream support to be completed. Link: https://github.com/openwrt/openwrt/pull/16730 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
94 lines
3.2 KiB
Diff
94 lines
3.2 KiB
Diff
From 7aa291962f4c3b7afb9a12fa60b406b95e5eacb4 Mon Sep 17 00:00:00 2001
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Thu, 27 Jun 2024 13:04:22 +0200
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Subject: [PATCH] dt-bindings: clock: airoha: Add reset support to EN7581 clock
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binding
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Introduce reset capability to EN7581 device-tree clock binding
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documentation. Add reset register mapping between misc scu and pb scu
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ones in order to follow the memory order. This change is not
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introducing any backward compatibility issue since the EN7581 dts is not
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upstream yet.
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Fixes: 0a382be005cf ("dt-bindings: clock: airoha: add EN7581 binding")
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Link: https://lore.kernel.org/r/28fef3e83062d5d71e7b4be4b47583f851a15bf8.1719485847.git.lorenzo@kernel.org
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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.../bindings/clock/airoha,en7523-scu.yaml | 25 ++++++-
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.../dt-bindings/reset/airoha,en7581-reset.h | 66 +++++++++++++++++++
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2 files changed, 90 insertions(+), 1 deletion(-)
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create mode 100644 include/dt-bindings/reset/airoha,en7581-reset.h
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--- /dev/null
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+++ b/include/dt-bindings/reset/airoha,en7581-reset.h
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@@ -0,0 +1,66 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+/*
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+ * Copyright (c) 2024 AIROHA Inc
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+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
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+ */
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+
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+#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
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+#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
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+
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+/* RST_CTRL2 */
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+#define EN7581_XPON_PHY_RST 0
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+#define EN7581_CPU_TIMER2_RST 1
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+#define EN7581_HSUART_RST 2
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+#define EN7581_UART4_RST 3
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+#define EN7581_UART5_RST 4
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+#define EN7581_I2C2_RST 5
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+#define EN7581_XSI_MAC_RST 6
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+#define EN7581_XSI_PHY_RST 7
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+#define EN7581_NPU_RST 8
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+#define EN7581_I2S_RST 9
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+#define EN7581_TRNG_RST 10
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+#define EN7581_TRNG_MSTART_RST 11
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+#define EN7581_DUAL_HSI0_RST 12
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+#define EN7581_DUAL_HSI1_RST 13
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+#define EN7581_HSI_RST 14
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+#define EN7581_DUAL_HSI0_MAC_RST 15
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+#define EN7581_DUAL_HSI1_MAC_RST 16
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+#define EN7581_HSI_MAC_RST 17
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+#define EN7581_WDMA_RST 18
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+#define EN7581_WOE0_RST 19
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+#define EN7581_WOE1_RST 20
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+#define EN7581_HSDMA_RST 21
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+#define EN7581_TDMA_RST 22
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+#define EN7581_EMMC_RST 23
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+#define EN7581_SOE_RST 24
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+#define EN7581_PCIE2_RST 25
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+#define EN7581_XFP_MAC_RST 26
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+#define EN7581_USB_HOST_P1_RST 27
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+#define EN7581_USB_HOST_P1_U3_PHY_RST 28
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+/* RST_CTRL1 */
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+#define EN7581_PCM1_ZSI_ISI_RST 29
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+#define EN7581_FE_PDMA_RST 30
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+#define EN7581_FE_QDMA_RST 31
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+#define EN7581_PCM_SPIWP_RST 32
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+#define EN7581_CRYPTO_RST 33
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+#define EN7581_TIMER_RST 34
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+#define EN7581_PCM1_RST 35
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+#define EN7581_UART_RST 36
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+#define EN7581_GPIO_RST 37
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+#define EN7581_GDMA_RST 38
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+#define EN7581_I2C_MASTER_RST 39
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+#define EN7581_PCM2_ZSI_ISI_RST 40
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+#define EN7581_SFC_RST 41
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+#define EN7581_UART2_RST 42
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+#define EN7581_GDMP_RST 43
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+#define EN7581_FE_RST 44
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+#define EN7581_USB_HOST_P0_RST 45
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+#define EN7581_GSW_RST 46
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+#define EN7581_SFC2_PCM_RST 47
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+#define EN7581_PCIE0_RST 48
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+#define EN7581_PCIE1_RST 49
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+#define EN7581_CPU_TIMER_RST 50
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+#define EN7581_PCIE_HB_RST 51
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+#define EN7581_XPON_MAC_RST 52
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+
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+#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */
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