mirror of
https://github.com/openwrt/openwrt.git
synced 2025-02-22 18:02:46 +00:00
93173aee96
Add initial support for new target with the initial patch for ethernet support using pending upstream patches for PCS UNIPHY, PPE and EDMA. Only initramfs currently working as support for new SPI/NAND implementation, USB, CPUFreq and other devices is still unfinished and needs to be evaluated. Link: https://github.com/openwrt/openwrt/pull/17725 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
97 lines
3.2 KiB
Diff
97 lines
3.2 KiB
Diff
From 14caaa7a23404cfee65a0d74b61d7998f762c70f Mon Sep 17 00:00:00 2001
|
|
From: Pavithra R <quic_pavir@quicinc.com>
|
|
Date: Wed, 6 Mar 2024 22:29:41 +0530
|
|
Subject: [PATCH 16/17] arm64: dts: qcom: Add EDMA node for IPQ9574
|
|
|
|
Add EDMA (Ethernet DMA) device tree node for IPQ9574 to
|
|
enable ethernet support.
|
|
|
|
Change-Id: I87d7c50f2485c8670948dce305000337f6499f8b
|
|
Signed-off-by: Pavithra R <quic_pavir@quicinc.com>
|
|
---
|
|
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 68 +++++++++++++++++++++++++++
|
|
1 file changed, 68 insertions(+)
|
|
|
|
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
|
|
index ef82935e7ef5..61f9a7ee7282 100644
|
|
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
|
|
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
|
|
@@ -939,6 +939,74 @@ &gcc SLAVE_NSSNOC_MEMNOC>,
|
|
"nssnoc_memnoc",
|
|
"memnoc_nssnoc",
|
|
"memnoc_nssnoc_1";
|
|
+
|
|
+ edma {
|
|
+ compatible = "qcom,ipq9574-edma";
|
|
+ clocks = <&nsscc NSS_CC_PPE_EDMA_CLK>,
|
|
+ <&nsscc NSS_CC_PPE_EDMA_CFG_CLK>;
|
|
+ clock-names = "edma",
|
|
+ "edma-cfg";
|
|
+ resets = <&nsscc EDMA_HW_RESET>;
|
|
+ reset-names = "edma_rst";
|
|
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "edma_txcmpl_8",
|
|
+ "edma_txcmpl_9",
|
|
+ "edma_txcmpl_10",
|
|
+ "edma_txcmpl_11",
|
|
+ "edma_txcmpl_12",
|
|
+ "edma_txcmpl_13",
|
|
+ "edma_txcmpl_14",
|
|
+ "edma_txcmpl_15",
|
|
+ "edma_txcmpl_16",
|
|
+ "edma_txcmpl_17",
|
|
+ "edma_txcmpl_18",
|
|
+ "edma_txcmpl_19",
|
|
+ "edma_txcmpl_20",
|
|
+ "edma_txcmpl_21",
|
|
+ "edma_txcmpl_22",
|
|
+ "edma_txcmpl_23",
|
|
+ "edma_txcmpl_24",
|
|
+ "edma_txcmpl_25",
|
|
+ "edma_txcmpl_26",
|
|
+ "edma_txcmpl_27",
|
|
+ "edma_txcmpl_28",
|
|
+ "edma_txcmpl_29",
|
|
+ "edma_txcmpl_30",
|
|
+ "edma_txcmpl_31",
|
|
+ "edma_rxdesc_20",
|
|
+ "edma_rxdesc_21",
|
|
+ "edma_rxdesc_22",
|
|
+ "edma_rxdesc_23",
|
|
+ "edma_misc";
|
|
+ };
|
|
};
|
|
};
|
|
|
|
--
|
|
2.45.2
|
|
|