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93173aee96
Add initial support for new target with the initial patch for ethernet support using pending upstream patches for PCS UNIPHY, PPE and EDMA. Only initramfs currently working as support for new SPI/NAND implementation, USB, CPUFreq and other devices is still unfinished and needs to be evaluated. Link: https://github.com/openwrt/openwrt/pull/17725 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
239 lines
8.5 KiB
Diff
239 lines
8.5 KiB
Diff
From 61881bae3ad9d961139e970f1aae75070cd45b5c Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Wed, 27 Dec 2023 14:11:40 +0800
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Subject: [PATCH 24/50] net: ethernet: qualcomm: Add PPE port control config
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1. Initialize and setup the physical port.
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2. Configure the default action as drop when the packet size
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is more than the configured MTU of physical port.
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Change-Id: Id98aea7b17556f85021905978b3403ca6d427557
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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---
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.../net/ethernet/qualcomm/ppe/ppe_config.c | 91 ++++++++++++++++++-
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.../net/ethernet/qualcomm/ppe/ppe_config.h | 11 +++
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drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 50 ++++++++++
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3 files changed, 151 insertions(+), 1 deletion(-)
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diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
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index a8e7a536a6e0..18296a449d4e 100644
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--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
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@@ -1238,6 +1238,50 @@ int ppe_servcode_config_set(struct ppe_device *ppe_dev, int servcode,
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return regmap_write(ppe_dev->regmap, reg, val);
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}
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+/**
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+ * ppe_counter_set - Set PPE port counter enabled or not
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+ * @ppe_dev: PPE device
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+ * @port: PPE port ID
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+ * @enable: Counter status
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+ *
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+ * PPE port counter is optionally configured as enabled or not.
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+ *
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+ * Return 0 on success, negative error code on failure.
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+ */
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+int ppe_counter_set(struct ppe_device *ppe_dev, int port, bool enable)
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+{
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+ u32 reg, val, mru_mtu_val[3];
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+ int ret;
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+
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+ reg = PPE_MRU_MTU_CTRL_TBL_ADDR + PPE_MRU_MTU_CTRL_TBL_INC * port;
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+ ret = regmap_bulk_read(ppe_dev->regmap, reg,
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+ mru_mtu_val, ARRAY_SIZE(mru_mtu_val));
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+ if (ret)
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+ return ret;
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+
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+ PPE_MRU_MTU_CTRL_SET_RX_CNT_EN(mru_mtu_val, enable);
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+ PPE_MRU_MTU_CTRL_SET_TX_CNT_EN(mru_mtu_val, enable);
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+ ret = regmap_bulk_write(ppe_dev->regmap, reg,
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+ mru_mtu_val, ARRAY_SIZE(mru_mtu_val));
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+ if (ret)
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+ return ret;
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+
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+ reg = PPE_MC_MTU_CTRL_TBL_ADDR + PPE_MC_MTU_CTRL_TBL_INC * port;
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+ val = FIELD_PREP(PPE_MC_MTU_CTRL_TBL_TX_CNT_EN, enable);
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+ ret = regmap_update_bits(ppe_dev->regmap, reg,
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+ PPE_MC_MTU_CTRL_TBL_TX_CNT_EN,
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+ val);
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+ if (ret)
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+ return ret;
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+
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+ reg = PPE_PORT_EG_VLAN_ADDR + PPE_PORT_EG_VLAN_INC * port;
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+ val = FIELD_PREP(PPE_PORT_EG_VLAN_TX_COUNTING_EN, enable);
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+
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+ return regmap_update_bits(ppe_dev->regmap, reg,
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+ PPE_PORT_EG_VLAN_TX_COUNTING_EN,
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+ val);
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+}
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+
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static int ppe_config_bm_threshold(struct ppe_device *ppe_dev, int bm_port_id,
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struct ppe_bm_port_config port_cfg)
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{
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@@ -1659,6 +1703,47 @@ static int ppe_servcode_init(struct ppe_device *ppe_dev)
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return ppe_servcode_config_set(ppe_dev, PPE_EDMA_SC_BYPASS_ID, servcode_cfg);
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}
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+/* Initialize PPE port configurations. */
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+static int ppe_port_ctrl_init(struct ppe_device *ppe_dev)
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+{
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+ u32 reg, val, mru_mtu_val[3];
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+ int i, ret;
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+
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+ for (i = 1; i < ppe_dev->num_ports; i++) {
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+ /* Enable PPE port counter */
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+ ret = ppe_counter_set(ppe_dev, i, true);
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+ if (ret)
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+ return ret;
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+
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+ reg = PPE_MRU_MTU_CTRL_TBL_ADDR + PPE_MRU_MTU_CTRL_TBL_INC * i;
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+ ret = regmap_bulk_read(ppe_dev->regmap, reg,
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+ mru_mtu_val, ARRAY_SIZE(mru_mtu_val));
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+ if (ret)
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+ return ret;
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+
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+ /* Drop the packet when the packet size is more than
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+ * the MTU or MRU of the physical PPE port.
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+ */
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+ PPE_MRU_MTU_CTRL_SET_MRU_CMD(mru_mtu_val, PPE_ACTION_DROP);
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+ PPE_MRU_MTU_CTRL_SET_MTU_CMD(mru_mtu_val, PPE_ACTION_DROP);
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+ ret = regmap_bulk_write(ppe_dev->regmap, reg,
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+ mru_mtu_val, ARRAY_SIZE(mru_mtu_val));
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+ if (ret)
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+ return ret;
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+
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+ reg = PPE_MC_MTU_CTRL_TBL_ADDR + PPE_MC_MTU_CTRL_TBL_INC * i;
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+ val = FIELD_PREP(PPE_MC_MTU_CTRL_TBL_MTU_CMD, PPE_ACTION_DROP);
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+ ret = regmap_update_bits(ppe_dev->regmap, reg,
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+ PPE_MC_MTU_CTRL_TBL_MTU_CMD,
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+ val);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ /* Enable CPU port counter. */
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+ return ppe_counter_set(ppe_dev, 0, true);
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+}
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+
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/* Initialize PPE device to handle traffic correctly. */
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static int ppe_dev_hw_init(struct ppe_device *ppe_dev)
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{
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@@ -1668,7 +1753,11 @@ static int ppe_dev_hw_init(struct ppe_device *ppe_dev)
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if (ret)
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return ret;
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- return ppe_servcode_init(ppe_dev);
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+ ret = ppe_servcode_init(ppe_dev);
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+ if (ret)
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+ return ret;
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+
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+ return ppe_port_ctrl_init(ppe_dev);
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}
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int ppe_hw_config(struct ppe_device *ppe_dev)
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diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_config.h b/drivers/net/ethernet/qualcomm/ppe/ppe_config.h
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index dcb557ed843c..7f5d92c39dd3 100644
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--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.h
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.h
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@@ -192,6 +192,16 @@ struct ppe_servcode_cfg {
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int offset_sel;
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};
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+/* The action of packet received by PPE can be forwarded, dropped, copied
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+ * to CPU (enter multicast queue), redirected to CPU (enter unicast queue).
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+ */
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+enum ppe_action_type {
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+ PPE_ACTION_FORWARD = 0,
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+ PPE_ACTION_DROP = 1,
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+ PPE_ACTION_COPY_TO_CPU = 2,
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+ PPE_ACTION_REDIRECT_TO_CPU = 3,
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+};
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+
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int ppe_hw_config(struct ppe_device *ppe_dev);
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int ppe_queue_scheduler_set(struct ppe_device *ppe_dev,
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int node_id, bool flow_level, int port,
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@@ -216,4 +226,5 @@ int ppe_port_resource_get(struct ppe_device *ppe_dev, int port, int type,
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int ppe_servcode_config_set(struct ppe_device *ppe_dev,
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int servcode,
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struct ppe_servcode_cfg cfg);
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+int ppe_counter_set(struct ppe_device *ppe_dev, int port, bool enable);
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#endif
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diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
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index 3122743af98d..e981a1c0e670 100644
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--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
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@@ -18,6 +18,11 @@
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#define PPE_BM_SCH_CTRL_SCH_OFFSET GENMASK(14, 8)
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#define PPE_BM_SCH_CTRL_SCH_EN BIT(31)
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+#define PPE_RX_FIFO_CFG_ADDR 0xb004
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+#define PPE_RX_FIFO_CFG_NUM 8
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+#define PPE_RX_FIFO_CFG_INC 4
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+#define PPE_RX_FIFO_CFG_THRSH GENMASK(2, 0)
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+
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#define PPE_BM_SCH_CFG_TBL_ADDR 0xc000
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#define PPE_BM_SCH_CFG_TBL_NUM 128
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#define PPE_BM_SCH_CFG_TBL_INC 0x10
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@@ -39,6 +44,17 @@
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#define PPE_SERVICE_SET_RX_CNT_EN(tbl_cfg, value) \
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u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_SERVICE_W1_RX_CNT_EN)
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+#define PPE_PORT_EG_VLAN_ADDR 0x20020
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+#define PPE_PORT_EG_VLAN_NUM 8
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+#define PPE_PORT_EG_VLAN_INC 4
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+#define PPE_PORT_EG_VLAN_VLAN_TYPE BIT(0)
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+#define PPE_PORT_EG_VLAN_CTAG_MODE GENMASK(2, 1)
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+#define PPE_PORT_EG_VLAN_STAG_MODE GENMASK(4, 3)
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+#define PPE_PORT_EG_VLAN_VSI_TAG_MODE_EN BIT(5)
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+#define PPE_PORT_EG_VLAN_PCP_PROP_CMD BIT(6)
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+#define PPE_PORT_EG_VLAN_DEI_PROP_CMD BIT(7)
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+#define PPE_PORT_EG_VLAN_TX_COUNTING_EN BIT(8)
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+
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#define PPE_EG_BRIDGE_CONFIG_ADDR 0x20044
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#define PPE_EG_BRIDGE_CONFIG_QUEUE_CNT_EN BIT(2)
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@@ -63,6 +79,40 @@
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#define PPE_EG_SERVICE_SET_TX_CNT_EN(tbl_cfg, value) \
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u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_EG_SERVICE_W1_TX_CNT_EN)
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+#define PPE_MC_MTU_CTRL_TBL_ADDR 0x60a00
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+#define PPE_MC_MTU_CTRL_TBL_NUM 8
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+#define PPE_MC_MTU_CTRL_TBL_INC 4
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+#define PPE_MC_MTU_CTRL_TBL_MTU GENMASK(13, 0)
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+#define PPE_MC_MTU_CTRL_TBL_MTU_CMD GENMASK(15, 14)
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+#define PPE_MC_MTU_CTRL_TBL_TX_CNT_EN BIT(16)
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+
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+/* PPE port control configuration, the MTU and MRU configs. */
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+#define PPE_MRU_MTU_CTRL_TBL_ADDR 0x65000
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+#define PPE_MRU_MTU_CTRL_TBL_NUM 256
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+#define PPE_MRU_MTU_CTRL_TBL_INC 0x10
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+#define PPE_MRU_MTU_CTRL_W0_MRU GENMASK(13, 0)
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+#define PPE_MRU_MTU_CTRL_W0_MRU_CMD GENMASK(15, 14)
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+#define PPE_MRU_MTU_CTRL_W0_MTU GENMASK(29, 16)
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+#define PPE_MRU_MTU_CTRL_W0_MTU_CMD GENMASK(31, 30)
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+#define PPE_MRU_MTU_CTRL_W1_RX_CNT_EN BIT(0)
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+#define PPE_MRU_MTU_CTRL_W1_TX_CNT_EN BIT(1)
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+#define PPE_MRU_MTU_CTRL_W1_SRC_PROFILE GENMASK(3, 2)
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+#define PPE_MRU_MTU_CTRL_W1_INNER_PREC_LOW BIT(31)
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+#define PPE_MRU_MTU_CTRL_W2_INNER_PREC_HIGH GENMASK(1, 0)
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+
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+#define PPE_MRU_MTU_CTRL_SET_MRU(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_MRU_MTU_CTRL_W0_MRU)
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+#define PPE_MRU_MTU_CTRL_SET_MRU_CMD(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_MRU_MTU_CTRL_W0_MRU_CMD)
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+#define PPE_MRU_MTU_CTRL_SET_MTU(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_MRU_MTU_CTRL_W0_MTU)
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+#define PPE_MRU_MTU_CTRL_SET_MTU_CMD(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_MRU_MTU_CTRL_W0_MTU_CMD)
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+#define PPE_MRU_MTU_CTRL_SET_RX_CNT_EN(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_MRU_MTU_CTRL_W1_RX_CNT_EN)
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+#define PPE_MRU_MTU_CTRL_SET_TX_CNT_EN(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_MRU_MTU_CTRL_W1_TX_CNT_EN)
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+
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#define PPE_IN_L2_SERVICE_TBL_ADDR 0x66000
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#define PPE_IN_L2_SERVICE_TBL_NUM 256
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#define PPE_IN_L2_SERVICE_TBL_INC 0x10
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--
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2.45.2
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