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93173aee96
Add initial support for new target with the initial patch for ethernet support using pending upstream patches for PCS UNIPHY, PPE and EDMA. Only initramfs currently working as support for new SPI/NAND implementation, USB, CPUFreq and other devices is still unfinished and needs to be evaluated. Link: https://github.com/openwrt/openwrt/pull/17725 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
325 lines
10 KiB
Diff
325 lines
10 KiB
Diff
From 049820d8a0c918cedd4524eda9abf750819ac901 Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Tue, 26 Dec 2023 18:19:30 +0800
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Subject: [PATCH 19/50] net: ethernet: qualcomm: Add PPE buffer manager
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configuration
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The BM (Buffer Management) config controls the pause frame generated
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on the PPE port. There are maximum 15 BM ports and 4 groups supported,
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all BM ports are assigned to group 0 by default. The number of hardware
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buffers configured for the port influence the threshold of the flow
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control for that port.
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Change-Id: Ifb1b69c89966cf5cab19f8e2661c64a4dc6230fe
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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---
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drivers/net/ethernet/qualcomm/ppe/Makefile | 2 +-
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drivers/net/ethernet/qualcomm/ppe/ppe.c | 5 +
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.../net/ethernet/qualcomm/ppe/ppe_config.c | 181 ++++++++++++++++++
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.../net/ethernet/qualcomm/ppe/ppe_config.h | 10 +
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drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 54 ++++++
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5 files changed, 251 insertions(+), 1 deletion(-)
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create mode 100644 drivers/net/ethernet/qualcomm/ppe/ppe_config.c
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create mode 100644 drivers/net/ethernet/qualcomm/ppe/ppe_config.h
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create mode 100644 drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
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diff --git a/drivers/net/ethernet/qualcomm/ppe/Makefile b/drivers/net/ethernet/qualcomm/ppe/Makefile
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index 63d50d3b4f2e..410a7bb54cfe 100644
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--- a/drivers/net/ethernet/qualcomm/ppe/Makefile
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+++ b/drivers/net/ethernet/qualcomm/ppe/Makefile
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@@ -4,4 +4,4 @@
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#
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obj-$(CONFIG_QCOM_PPE) += qcom-ppe.o
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-qcom-ppe-objs := ppe.o
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+qcom-ppe-objs := ppe.o ppe_config.o
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diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe.c b/drivers/net/ethernet/qualcomm/ppe/ppe.c
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index 14998ac771c7..443706291ce0 100644
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--- a/drivers/net/ethernet/qualcomm/ppe/ppe.c
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe.c
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@@ -15,6 +15,7 @@
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#include <linux/reset.h>
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#include "ppe.h"
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+#include "ppe_config.h"
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#define PPE_PORT_MAX 8
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#define PPE_CLK_RATE 353000000
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@@ -201,6 +202,10 @@ static int qcom_ppe_probe(struct platform_device *pdev)
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if (ret)
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return dev_err_probe(dev, ret, "PPE clock config failed\n");
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+ ret = ppe_hw_config(ppe_dev);
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+ if (ret)
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+ return dev_err_probe(dev, ret, "PPE HW config failed\n");
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+
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platform_set_drvdata(pdev, ppe_dev);
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return 0;
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diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
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new file mode 100644
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index 000000000000..0ba4efdfd509
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--- /dev/null
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
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@@ -0,0 +1,181 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+/*
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+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+/* PPE HW initialization configs such as BM(buffer management),
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+ * QM(queue management) and scheduler configs.
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+ */
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+
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+#include <linux/bitfield.h>
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+#include <linux/bits.h>
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+#include <linux/device.h>
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+#include <linux/regmap.h>
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+
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+#include "ppe.h"
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+#include "ppe_config.h"
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+#include "ppe_regs.h"
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+
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+/**
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+ * struct ppe_bm_port_config - PPE BM port configuration.
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+ * @port_id_start: The fist BM port ID to configure.
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+ * @port_id_end: The last BM port ID to configure.
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+ * @pre_alloc: BM port dedicated buffer number.
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+ * @in_fly_buf: Buffer number for receiving the packet after pause frame sent.
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+ * @ceil: Ceil to generate the back pressure.
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+ * @weight: Weight value.
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+ * @resume_offset: Resume offset from the threshold value.
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+ * @resume_ceil: Ceil to resume from the back pressure state.
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+ * @dynamic: Dynamic threshold used or not.
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+ *
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+ * The is for configuring the threshold that impacts the port
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+ * flow control.
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+ */
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+struct ppe_bm_port_config {
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+ unsigned int port_id_start;
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+ unsigned int port_id_end;
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+ unsigned int pre_alloc;
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+ unsigned int in_fly_buf;
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+ unsigned int ceil;
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+ unsigned int weight;
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+ unsigned int resume_offset;
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+ unsigned int resume_ceil;
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+ bool dynamic;
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+};
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+
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+static int ipq9574_ppe_bm_group_config = 1550;
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+static struct ppe_bm_port_config ipq9574_ppe_bm_port_config[] = {
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+ {
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+ .port_id_start = 0,
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+ .port_id_end = 0,
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+ .pre_alloc = 0,
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+ .in_fly_buf = 100,
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+ .ceil = 1146,
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+ .weight = 7,
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+ .resume_offset = 8,
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+ .resume_ceil = 0,
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+ .dynamic = true,
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+ },
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+ {
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+ .port_id_start = 1,
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+ .port_id_end = 7,
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+ .pre_alloc = 0,
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+ .in_fly_buf = 100,
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+ .ceil = 250,
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+ .weight = 4,
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+ .resume_offset = 36,
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+ .resume_ceil = 0,
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+ .dynamic = true,
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+ },
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+ {
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+ .port_id_start = 8,
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+ .port_id_end = 13,
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+ .pre_alloc = 0,
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+ .in_fly_buf = 128,
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+ .ceil = 250,
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+ .weight = 4,
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+ .resume_offset = 36,
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+ .resume_ceil = 0,
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+ .dynamic = true,
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+ },
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+ {
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+ .port_id_start = 14,
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+ .port_id_end = 14,
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+ .pre_alloc = 0,
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+ .in_fly_buf = 40,
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+ .ceil = 250,
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+ .weight = 4,
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+ .resume_offset = 36,
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+ .resume_ceil = 0,
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+ .dynamic = true,
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+ },
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+};
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+
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+static int ppe_config_bm_threshold(struct ppe_device *ppe_dev, int bm_port_id,
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+ struct ppe_bm_port_config port_cfg)
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+{
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+ u32 reg, val, bm_fc_val[2];
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+ int ret;
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+
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+ /* Configure BM flow control related threshold */
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+ PPE_BM_PORT_FC_SET_WEIGHT(bm_fc_val, port_cfg.weight);
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+ PPE_BM_PORT_FC_SET_RESUME_OFFSET(bm_fc_val, port_cfg.resume_offset);
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+ PPE_BM_PORT_FC_SET_RESUME_THRESHOLD(bm_fc_val, port_cfg.resume_ceil);
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+ PPE_BM_PORT_FC_SET_DYNAMIC(bm_fc_val, port_cfg.dynamic);
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+ PPE_BM_PORT_FC_SET_REACT_LIMIT(bm_fc_val, port_cfg.in_fly_buf);
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+ PPE_BM_PORT_FC_SET_PRE_ALLOC(bm_fc_val, port_cfg.pre_alloc);
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+
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+ /* Ceiling is divided into the different register word. */
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+ val = FIELD_GET(GENMASK(2, 0), port_cfg.ceil);
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+ PPE_BM_PORT_FC_SET_CEILING_LOW(bm_fc_val, val);
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+ val = FIELD_GET(GENMASK(10, 3), port_cfg.ceil);
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+ PPE_BM_PORT_FC_SET_CEILING_HIGH(bm_fc_val, val);
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+
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+ reg = PPE_BM_PORT_FC_CFG_ADDR + PPE_BM_PORT_FC_CFG_INC * bm_port_id;
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+ ret = regmap_bulk_write(ppe_dev->regmap, reg,
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+ bm_fc_val, ARRAY_SIZE(bm_fc_val));
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+ if (ret)
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+ return ret;
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+
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+ /* Assign the default group ID 0 to the BM port */
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+ val = FIELD_PREP(PPE_BM_PORT_GROUP_ID_SHARED_GROUP_ID, 0);
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+ reg = PPE_BM_PORT_GROUP_ID_ADDR + PPE_BM_PORT_GROUP_ID_INC * bm_port_id;
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+ ret = regmap_update_bits(ppe_dev->regmap, reg,
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+ PPE_BM_PORT_GROUP_ID_SHARED_GROUP_ID,
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+ val);
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+ if (ret)
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+ return ret;
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+
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+ /* Enable BM port flow control */
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+ val = FIELD_PREP(PPE_BM_PORT_FC_MODE_EN, true);
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+ reg = PPE_BM_PORT_FC_MODE_ADDR + PPE_BM_PORT_FC_MODE_INC * bm_port_id;
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+
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+ return regmap_update_bits(ppe_dev->regmap, reg,
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+ PPE_BM_PORT_FC_MODE_EN,
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+ val);
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+}
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+
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+/* Configure the buffer threshold for the port flow control function. */
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+static int ppe_config_bm(struct ppe_device *ppe_dev)
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+{
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+ unsigned int i, bm_port_id, port_cfg_cnt;
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+ struct ppe_bm_port_config *port_cfg;
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+ u32 reg, val;
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+ int ret;
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+
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+ /* Configure the buffer number of group 0 by default. The buffer
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+ * number of group 1-3 is cleared to 0 after PPE reset on the probe
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+ * of PPE driver.
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+ */
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+ reg = PPE_BM_SHARED_GROUP_CFG_ADDR;
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+ val = FIELD_PREP(PPE_BM_SHARED_GROUP_CFG_SHARED_LIMIT,
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+ ipq9574_ppe_bm_group_config);
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+ ret = regmap_update_bits(ppe_dev->regmap, reg,
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+ PPE_BM_SHARED_GROUP_CFG_SHARED_LIMIT,
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+ val);
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+ if (ret)
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+ goto bm_config_fail;
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+
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+ port_cfg = ipq9574_ppe_bm_port_config;
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+ port_cfg_cnt = ARRAY_SIZE(ipq9574_ppe_bm_port_config);
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+ for (i = 0; i < port_cfg_cnt; i++) {
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+ for (bm_port_id = port_cfg[i].port_id_start;
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+ bm_port_id <= port_cfg[i].port_id_end; bm_port_id++) {
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+ ret = ppe_config_bm_threshold(ppe_dev, bm_port_id,
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+ port_cfg[i]);
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+ if (ret)
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+ goto bm_config_fail;
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+ }
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+ }
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+
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+ return 0;
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+
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+bm_config_fail:
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+ dev_err(ppe_dev->dev, "PPE BM config error %d\n", ret);
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+ return ret;
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+}
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+
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+int ppe_hw_config(struct ppe_device *ppe_dev)
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+{
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+ return ppe_config_bm(ppe_dev);
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+}
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diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_config.h b/drivers/net/ethernet/qualcomm/ppe/ppe_config.h
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new file mode 100644
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index 000000000000..7e66019de799
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--- /dev/null
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.h
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@@ -0,0 +1,10 @@
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+/* SPDX-License-Identifier: GPL-2.0-only
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+ *
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+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+#ifndef __PPE_CONFIG_H__
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+#define __PPE_CONFIG_H__
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+
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+int ppe_hw_config(struct ppe_device *ppe_dev);
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+#endif
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diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
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new file mode 100644
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index 000000000000..bf25e0acc0f6
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--- /dev/null
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
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@@ -0,0 +1,54 @@
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+/* SPDX-License-Identifier: GPL-2.0-only
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+ *
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+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+/* PPE hardware register and table declarations. */
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+#ifndef __PPE_REGS_H__
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+#define __PPE_REGS_H__
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+
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+/* There are 15 BM ports and 4 BM groups supported by PPE,
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+ * BM port (0-7) is matched to EDMA port 0, BM port (8-13) is matched
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+ * to PPE physical port 1-6, BM port 14 is matched to EIP.
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+ */
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+#define PPE_BM_PORT_FC_MODE_ADDR 0x600100
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+#define PPE_BM_PORT_FC_MODE_INC 0x4
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+#define PPE_BM_PORT_FC_MODE_EN BIT(0)
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+
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+#define PPE_BM_PORT_GROUP_ID_ADDR 0x600180
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+#define PPE_BM_PORT_GROUP_ID_INC 0x4
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+#define PPE_BM_PORT_GROUP_ID_SHARED_GROUP_ID GENMASK(1, 0)
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+
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+#define PPE_BM_SHARED_GROUP_CFG_ADDR 0x600290
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+#define PPE_BM_SHARED_GROUP_CFG_INC 0x4
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+#define PPE_BM_SHARED_GROUP_CFG_SHARED_LIMIT GENMASK(10, 0)
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+
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+#define PPE_BM_PORT_FC_CFG_ADDR 0x601000
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+#define PPE_BM_PORT_FC_CFG_INC 0x10
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+#define PPE_BM_PORT_FC_W0_REACT_LIMIT GENMASK(8, 0)
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+#define PPE_BM_PORT_FC_W0_RESUME_THRESHOLD GENMASK(17, 9)
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+#define PPE_BM_PORT_FC_W0_RESUME_OFFSET GENMASK(28, 18)
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+#define PPE_BM_PORT_FC_W0_CEILING_LOW GENMASK(31, 29)
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+#define PPE_BM_PORT_FC_W1_CEILING_HIGH GENMASK(7, 0)
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+#define PPE_BM_PORT_FC_W1_WEIGHT GENMASK(10, 8)
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+#define PPE_BM_PORT_FC_W1_DYNAMIC BIT(11)
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+#define PPE_BM_PORT_FC_W1_PRE_ALLOC GENMASK(22, 12)
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+
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+#define PPE_BM_PORT_FC_SET_REACT_LIMIT(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_BM_PORT_FC_W0_REACT_LIMIT)
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+#define PPE_BM_PORT_FC_SET_RESUME_THRESHOLD(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_BM_PORT_FC_W0_RESUME_THRESHOLD)
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+#define PPE_BM_PORT_FC_SET_RESUME_OFFSET(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_BM_PORT_FC_W0_RESUME_OFFSET)
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+#define PPE_BM_PORT_FC_SET_CEILING_LOW(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)tbl_cfg, value, PPE_BM_PORT_FC_W0_CEILING_LOW)
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+#define PPE_BM_PORT_FC_SET_CEILING_HIGH(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_BM_PORT_FC_W1_CEILING_HIGH)
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+#define PPE_BM_PORT_FC_SET_WEIGHT(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_BM_PORT_FC_W1_WEIGHT)
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+#define PPE_BM_PORT_FC_SET_DYNAMIC(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_BM_PORT_FC_W1_DYNAMIC)
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+#define PPE_BM_PORT_FC_SET_PRE_ALLOC(tbl_cfg, value) \
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+ u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_BM_PORT_FC_W1_PRE_ALLOC)
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+
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+#endif
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--
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2.45.2
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