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93173aee96
Add initial support for new target with the initial patch for ethernet support using pending upstream patches for PCS UNIPHY, PPE and EDMA. Only initramfs currently working as support for new SPI/NAND implementation, USB, CPUFreq and other devices is still unfinished and needs to be evaluated. Link: https://github.com/openwrt/openwrt/pull/17725 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
101 lines
3.6 KiB
Diff
101 lines
3.6 KiB
Diff
From 23f3550c387246025ed2971989b747a5936bf080 Mon Sep 17 00:00:00 2001
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From: Lei Wei <quic_leiwei@quicinc.com>
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Date: Tue, 9 Apr 2024 01:07:22 +0800
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Subject: [PATCH 14/50] net:pcs: Add 1000BASEX interface mode support to IPQ
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UNIPHY PCS driver
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1000BASEX is used when PCS connects with a 1G SFP module.
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Change-Id: Ied7298de3c1ecba74e6457a07fdd6b3ceab79728
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Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
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---
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drivers/net/pcs/pcs-qcom-ipq-uniphy.c | 23 +++++++++++++++++++++++
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1 file changed, 23 insertions(+)
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diff --git a/drivers/net/pcs/pcs-qcom-ipq-uniphy.c b/drivers/net/pcs/pcs-qcom-ipq-uniphy.c
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index ed9c55a6c0fa..820d197744e8 100644
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--- a/drivers/net/pcs/pcs-qcom-ipq-uniphy.c
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+++ b/drivers/net/pcs/pcs-qcom-ipq-uniphy.c
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@@ -27,6 +27,9 @@
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#define PCS_MODE_PSGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x2)
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#define PCS_MODE_SGMII_PLUS FIELD_PREP(PCS_MODE_SEL_MASK, 0x8)
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#define PCS_MODE_XPCS FIELD_PREP(PCS_MODE_SEL_MASK, 0x10)
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+#define PCS_MODE_SGMII_CTRL_MASK GENMASK(6, 4)
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+#define PCS_MODE_SGMII_CTRL_1000BASEX FIELD_PREP(PCS_MODE_SGMII_CTRL_MASK, \
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+ 0x0)
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#define PCS_MODE_AN_MODE BIT(0)
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#define PCS_CHANNEL_CTRL(x) (0x480 + 0x18 * (x))
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@@ -392,6 +395,13 @@ static int ipq_unipcs_config_mode(struct ipq_uniphy_pcs *qunipcs,
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PCS_MODE_SEL_MASK | PCS_MODE_AN_MODE,
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PCS_MODE_PSGMII);
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break;
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+ case PHY_INTERFACE_MODE_1000BASEX:
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+ ipq_unipcs_reg_modify32(qunipcs, PCS_MODE_CTRL,
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+ PCS_MODE_SEL_MASK |
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+ PCS_MODE_SGMII_CTRL_MASK,
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+ PCS_MODE_SGMII |
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+ PCS_MODE_SGMII_CTRL_1000BASEX);
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+ break;
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case PHY_INTERFACE_MODE_2500BASEX:
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rate = 312500000;
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ipq_unipcs_reg_modify32(qunipcs, PCS_MODE_CTRL,
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@@ -620,6 +630,7 @@ ipq_unipcs_link_up_clock_rate_set(struct ipq_uniphy_pcs_ch *qunipcs_ch,
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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case PHY_INTERFACE_MODE_PSGMII:
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+ case PHY_INTERFACE_MODE_1000BASEX:
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rate = ipq_unipcs_clock_rate_get_gmii(speed);
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break;
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case PHY_INTERFACE_MODE_2500BASEX:
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@@ -765,6 +776,10 @@ static void ipq_unipcs_get_state(struct phylink_pcs *pcs,
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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case PHY_INTERFACE_MODE_PSGMII:
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+ case PHY_INTERFACE_MODE_1000BASEX:
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+ /* SGMII and 1000BASEX in-band autoneg word format are decoded
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+ * by PCS hardware and both placed to the same status register.
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+ */
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ipq_unipcs_get_state_sgmii(qunipcs, channel, state);
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break;
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case PHY_INTERFACE_MODE_2500BASEX:
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@@ -802,6 +817,7 @@ static int ipq_unipcs_config(struct phylink_pcs *pcs,
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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case PHY_INTERFACE_MODE_PSGMII:
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+ case PHY_INTERFACE_MODE_1000BASEX:
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return ipq_unipcs_config_sgmii(qunipcs, channel,
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neg_mode, interface);
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case PHY_INTERFACE_MODE_2500BASEX:
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@@ -818,6 +834,11 @@ static int ipq_unipcs_config(struct phylink_pcs *pcs,
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};
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}
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+static void qcom_ipq_unipcs_an_restart(struct phylink_pcs *pcs)
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+{
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+ /* Currently not used */
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+}
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+
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static void ipq_unipcs_link_up(struct phylink_pcs *pcs,
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unsigned int neg_mode,
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phy_interface_t interface,
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@@ -835,6 +856,7 @@ static void ipq_unipcs_link_up(struct phylink_pcs *pcs,
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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case PHY_INTERFACE_MODE_PSGMII:
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+ case PHY_INTERFACE_MODE_1000BASEX:
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ipq_unipcs_link_up_config_sgmii(qunipcs, channel,
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neg_mode, speed);
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break;
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@@ -858,6 +880,7 @@ static const struct phylink_pcs_ops ipq_unipcs_phylink_ops = {
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.pcs_validate = ipq_unipcs_validate,
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.pcs_get_state = ipq_unipcs_get_state,
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.pcs_config = ipq_unipcs_config,
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+ .pcs_an_restart = qcom_ipq_unipcs_an_restart,
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.pcs_link_up = ipq_unipcs_link_up,
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};
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--
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2.45.2
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