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93173aee96
Add initial support for new target with the initial patch for ethernet support using pending upstream patches for PCS UNIPHY, PPE and EDMA. Only initramfs currently working as support for new SPI/NAND implementation, USB, CPUFreq and other devices is still unfinished and needs to be evaluated. Link: https://github.com/openwrt/openwrt/pull/17725 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
145 lines
2.8 KiB
Diff
145 lines
2.8 KiB
Diff
From 968c5e8220209eb2185654f01748c349515a3b8e Mon Sep 17 00:00:00 2001
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From: Md Sadre Alam <quic_mdalam@quicinc.com>
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Date: Thu, 15 Feb 2024 12:26:40 +0530
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Subject: [PATCH v10 7/8] arm64: dts: qcom: ipq9574: Add SPI nand support
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Add SPI NAND support for ipq9574 SoC.
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Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
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---
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Change in [v10]
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* No change
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Change in [v9]
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* No change
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Change in [v8]
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* No change
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Change in [v7]
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* No change
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Change in [v6]
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* No change
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Change in [v5]
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* No change
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Change in [v4]
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* No change
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Change in [v3]
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* Updated gpio number as per pin control driver
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* Fixed alignment issue
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Change in [v2]
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* Added initial enablement for spi-nand
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Change in [v1]
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* Posted as RFC patch for design review
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.../boot/dts/qcom/ipq9574-rdp-common.dtsi | 43 +++++++++++++++++++
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arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 ++++++++++++
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2 files changed, 70 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
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+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
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@@ -121,6 +121,49 @@
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bias-pull-down;
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};
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};
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+
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+ qpic_snand_default_state: qpic-snand-default-state {
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+ clock-pins {
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+ pins = "gpio5";
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+ function = "qspi_clk";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+
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+ cs-pins {
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+ pins = "gpio4";
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+ function = "qspi_cs";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+
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+ data-pins {
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+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
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+ function = "qspi_data";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ };
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+};
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+
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+&qpic_bam {
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+ status = "okay";
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+};
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+
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+&qpic_nand {
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+ pinctrl-0 = <&qpic_snand_default_state>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+
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+ flash@0 {
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+ compatible = "spi-nand";
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+ reg = <0>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ nand-ecc-engine = <&qpic_nand>;
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+ nand-ecc-strength = <4>;
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+ nand-ecc-step-size = <512>;
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+ };
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};
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&usb_0_dwc3 {
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--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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@@ -300,6 +300,33 @@
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reg = <0x01937000 0x21000>;
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};
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+ qpic_bam: dma-controller@7984000 {
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+ compatible = "qcom,bam-v1.7.0";
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+ reg = <0x7984000 0x1c000>;
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+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_QPIC_AHB_CLK>;
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+ clock-names = "bam_clk";
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+ #dma-cells = <1>;
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+ qcom,ee = <0>;
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+ status = "disabled";
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+ };
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+
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+ qpic_nand: spi@79b0000 {
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+ compatible = "qcom,spi-qpic-snand", "qcom,ipq9574-nand";
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+ reg = <0x79b0000 0x10000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ clocks = <&gcc GCC_QPIC_CLK>,
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+ <&gcc GCC_QPIC_AHB_CLK>,
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+ <&gcc GCC_QPIC_IO_MACRO_CLK>;
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+ clock-names = "core", "aon", "iom";
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+ dmas = <&qpic_bam 0>,
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+ <&qpic_bam 1>,
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+ <&qpic_bam 2>;
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+ dma-names = "tx", "rx", "cmd";
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+ status = "disabled";
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+ };
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+
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sdhc_1: mmc@7804000 {
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compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
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reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
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