mirror of
https://github.com/openwrt/openwrt.git
synced 2025-02-22 10:01:03 +00:00
7333c694e3
Update patch with upstream version and automatically refresh with make target/linux/refresh. Also backport one additional fix patch for NAND patch and drop a patch merged upstream. Link: https://github.com/openwrt/openwrt/pull/17725 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
142 lines
4.7 KiB
Diff
142 lines
4.7 KiB
Diff
From c0f1cbf795095c21b92a46fa1dc47a7b787ce538 Mon Sep 17 00:00:00 2001
|
|
From: Luo Jie <quic_luoj@quicinc.com>
|
|
Date: Fri, 3 Jan 2025 15:31:34 +0800
|
|
Subject: [PATCH 1/3] dt-bindings: clock: qcom: Add CMN PLL clock controller
|
|
for IPQ SoC
|
|
|
|
The CMN PLL controller provides clocks to networking hardware blocks
|
|
and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the
|
|
on-chip Wi-Fi, and produces output clocks at fixed rates. These output
|
|
rates are predetermined, and are unrelated to the input clock rate.
|
|
The primary purpose of CMN PLL is to supply clocks to the networking
|
|
hardware such as PPE (packet process engine), PCS and the externally
|
|
connected switch or PHY device. The CMN PLL block also outputs fixed
|
|
rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep
|
|
clock supplied to GCC.
|
|
|
|
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
|
|
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com
|
|
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
---
|
|
.../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 77 +++++++++++++++++++
|
|
include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 22 ++++++
|
|
2 files changed, 99 insertions(+)
|
|
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
|
|
create mode 100644 include/dt-bindings/clock/qcom,ipq-cmn-pll.h
|
|
|
|
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
|
|
new file mode 100644
|
|
index 000000000000..f869b3739be8
|
|
--- /dev/null
|
|
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
|
|
@@ -0,0 +1,77 @@
|
|
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
|
+%YAML 1.2
|
|
+---
|
|
+$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
|
|
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
+
|
|
+title: Qualcomm CMN PLL Clock Controller on IPQ SoC
|
|
+
|
|
+maintainers:
|
|
+ - Bjorn Andersson <andersson@kernel.org>
|
|
+ - Luo Jie <quic_luoj@quicinc.com>
|
|
+
|
|
+description:
|
|
+ The CMN (or common) PLL clock controller expects a reference
|
|
+ input clock. This reference clock is from the on-board Wi-Fi.
|
|
+ The CMN PLL supplies a number of fixed rate output clocks to
|
|
+ the devices providing networking functions and to GCC. These
|
|
+ networking hardware include PPE (packet process engine), PCS
|
|
+ and the externally connected switch or PHY devices. The CMN
|
|
+ PLL block also outputs fixed rate clocks to GCC. The PLL's
|
|
+ primary function is to enable fixed rate output clocks for
|
|
+ networking hardware functions used with the IPQ SoC.
|
|
+
|
|
+properties:
|
|
+ compatible:
|
|
+ enum:
|
|
+ - qcom,ipq9574-cmn-pll
|
|
+
|
|
+ reg:
|
|
+ maxItems: 1
|
|
+
|
|
+ clocks:
|
|
+ items:
|
|
+ - description: The reference clock. The supported clock rates include
|
|
+ 25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.
|
|
+ - description: The AHB clock
|
|
+ - description: The SYS clock
|
|
+ description:
|
|
+ The reference clock is the source clock of CMN PLL, which is from the
|
|
+ Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
|
|
+ clock registers.
|
|
+
|
|
+ clock-names:
|
|
+ items:
|
|
+ - const: ref
|
|
+ - const: ahb
|
|
+ - const: sys
|
|
+
|
|
+ "#clock-cells":
|
|
+ const: 1
|
|
+
|
|
+required:
|
|
+ - compatible
|
|
+ - reg
|
|
+ - clocks
|
|
+ - clock-names
|
|
+ - "#clock-cells"
|
|
+
|
|
+additionalProperties: false
|
|
+
|
|
+examples:
|
|
+ - |
|
|
+ #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
|
|
+ #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
|
|
+
|
|
+ cmn_pll: clock-controller@9b000 {
|
|
+ compatible = "qcom,ipq9574-cmn-pll";
|
|
+ reg = <0x0009b000 0x800>;
|
|
+ clocks = <&cmn_pll_ref_clk>,
|
|
+ <&gcc GCC_CMN_12GPLL_AHB_CLK>,
|
|
+ <&gcc GCC_CMN_12GPLL_SYS_CLK>;
|
|
+ clock-names = "ref", "ahb", "sys";
|
|
+ #clock-cells = <1>;
|
|
+ assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
|
|
+ assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
|
|
+ };
|
|
+...
|
|
diff --git a/include/dt-bindings/clock/qcom,ipq-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
|
|
new file mode 100644
|
|
index 000000000000..936e92b3b62c
|
|
--- /dev/null
|
|
+++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
|
|
@@ -0,0 +1,22 @@
|
|
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
|
+/*
|
|
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
|
+ */
|
|
+
|
|
+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
|
|
+#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
|
|
+
|
|
+/* CMN PLL core clock. */
|
|
+#define CMN_PLL_CLK 0
|
|
+
|
|
+/* The output clocks from CMN PLL of IPQ9574. */
|
|
+#define XO_24MHZ_CLK 1
|
|
+#define SLEEP_32KHZ_CLK 2
|
|
+#define PCS_31P25MHZ_CLK 3
|
|
+#define NSS_1200MHZ_CLK 4
|
|
+#define PPE_353MHZ_CLK 5
|
|
+#define ETH0_50MHZ_CLK 6
|
|
+#define ETH1_50MHZ_CLK 7
|
|
+#define ETH2_50MHZ_CLK 8
|
|
+#define ETH_25MHZ_CLK 9
|
|
+#endif
|
|
--
|
|
2.47.1
|
|
|