mirror of
https://github.com/openwrt/openwrt.git
synced 2025-02-22 18:02:46 +00:00
93173aee96
Add initial support for new target with the initial patch for ethernet support using pending upstream patches for PCS UNIPHY, PPE and EDMA. Only initramfs currently working as support for new SPI/NAND implementation, USB, CPUFreq and other devices is still unfinished and needs to be evaluated. Link: https://github.com/openwrt/openwrt/pull/17725 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
135 lines
3.9 KiB
Diff
135 lines
3.9 KiB
Diff
From a8fe85d40ffe5ec0fd2f557932ffee902be35b38 Mon Sep 17 00:00:00 2001
|
|
From: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
Date: Tue, 30 Apr 2024 23:07:44 -0500
|
|
Subject: [PATCH] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks
|
|
|
|
The IPQ9574 has four PCIe "pipe" clocks. These clocks are required by
|
|
PCIe PHYs. Port the pipe clocks from the downstream 5.4 kernel.
|
|
|
|
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
|
Link: https://lore.kernel.org/r/20240501040800.1542805-3-mr.nuke.me@gmail.com
|
|
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
---
|
|
drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++
|
|
1 file changed, 76 insertions(+)
|
|
|
|
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
|
|
index 0a3f846695b8..bc3e17f34295 100644
|
|
--- a/drivers/clk/qcom/gcc-ipq9574.c
|
|
+++ b/drivers/clk/qcom/gcc-ipq9574.c
|
|
@@ -1569,6 +1569,24 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = {
|
|
},
|
|
};
|
|
|
|
+static struct clk_branch gcc_pcie0_pipe_clk = {
|
|
+ .halt_reg = 0x28044,
|
|
+ .halt_check = BRANCH_HALT_DELAY,
|
|
+ .clkr = {
|
|
+ .enable_reg = 0x28044,
|
|
+ .enable_mask = BIT(0),
|
|
+ .hw.init = &(const struct clk_init_data) {
|
|
+ .name = "gcc_pcie0_pipe_clk",
|
|
+ .parent_hws = (const struct clk_hw *[]) {
|
|
+ &pcie0_pipe_clk_src.clkr.hw
|
|
+ },
|
|
+ .num_parents = 1,
|
|
+ .flags = CLK_SET_RATE_PARENT,
|
|
+ .ops = &clk_branch2_ops,
|
|
+ },
|
|
+ },
|
|
+};
|
|
+
|
|
static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
|
|
.reg = 0x29064,
|
|
.clkr = {
|
|
@@ -1583,6 +1601,24 @@ static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
|
|
},
|
|
};
|
|
|
|
+static struct clk_branch gcc_pcie1_pipe_clk = {
|
|
+ .halt_reg = 0x29044,
|
|
+ .halt_check = BRANCH_HALT_DELAY,
|
|
+ .clkr = {
|
|
+ .enable_reg = 0x29044,
|
|
+ .enable_mask = BIT(0),
|
|
+ .hw.init = &(const struct clk_init_data) {
|
|
+ .name = "gcc_pcie1_pipe_clk",
|
|
+ .parent_hws = (const struct clk_hw *[]) {
|
|
+ &pcie1_pipe_clk_src.clkr.hw
|
|
+ },
|
|
+ .num_parents = 1,
|
|
+ .flags = CLK_SET_RATE_PARENT,
|
|
+ .ops = &clk_branch2_ops,
|
|
+ },
|
|
+ },
|
|
+};
|
|
+
|
|
static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
|
|
.reg = 0x2a064,
|
|
.clkr = {
|
|
@@ -1597,6 +1633,24 @@ static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
|
|
},
|
|
};
|
|
|
|
+static struct clk_branch gcc_pcie2_pipe_clk = {
|
|
+ .halt_reg = 0x2a044,
|
|
+ .halt_check = BRANCH_HALT_DELAY,
|
|
+ .clkr = {
|
|
+ .enable_reg = 0x2a044,
|
|
+ .enable_mask = BIT(0),
|
|
+ .hw.init = &(const struct clk_init_data) {
|
|
+ .name = "gcc_pcie2_pipe_clk",
|
|
+ .parent_hws = (const struct clk_hw *[]) {
|
|
+ &pcie2_pipe_clk_src.clkr.hw
|
|
+ },
|
|
+ .num_parents = 1,
|
|
+ .flags = CLK_SET_RATE_PARENT,
|
|
+ .ops = &clk_branch2_ops,
|
|
+ },
|
|
+ },
|
|
+};
|
|
+
|
|
static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
|
|
.reg = 0x2b064,
|
|
.clkr = {
|
|
@@ -1611,6 +1665,24 @@ static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
|
|
},
|
|
};
|
|
|
|
+static struct clk_branch gcc_pcie3_pipe_clk = {
|
|
+ .halt_reg = 0x2b044,
|
|
+ .halt_check = BRANCH_HALT_DELAY,
|
|
+ .clkr = {
|
|
+ .enable_reg = 0x2b044,
|
|
+ .enable_mask = BIT(0),
|
|
+ .hw.init = &(const struct clk_init_data) {
|
|
+ .name = "gcc_pcie3_pipe_clk",
|
|
+ .parent_hws = (const struct clk_hw *[]) {
|
|
+ &pcie3_pipe_clk_src.clkr.hw
|
|
+ },
|
|
+ .num_parents = 1,
|
|
+ .flags = CLK_SET_RATE_PARENT,
|
|
+ .ops = &clk_branch2_ops,
|
|
+ },
|
|
+ },
|
|
+};
|
|
+
|
|
static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
|
|
F(24000000, P_XO, 1, 0, 0),
|
|
F(100000000, P_GPLL0, 8, 0, 0),
|
|
@@ -4141,6 +4213,10 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
|
|
[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
|
|
[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
|
|
[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
|
|
+ [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
|
|
+ [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
|
|
+ [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
|
|
+ [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
|
|
};
|
|
|
|
static const struct qcom_reset_map gcc_ipq9574_resets[] = {
|
|
--
|
|
2.45.2
|
|
|