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91 lines
2.4 KiB
Diff
91 lines
2.4 KiB
Diff
From 9997227090cf529675aeb775585ec9f6c2f0f131 Mon Sep 17 00:00:00 2001
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From: Randy Dunlap <rdunlap@infradead.org>
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Date: Thu, 19 Aug 2021 15:32:37 -0700
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Subject: [PATCH 114/247] clk: at91: sama7g5: remove all kernel-doc &
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kernel-doc warnings
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Remove all "/**" kernel-doc markers from sama7g5.c since they are
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all internal to this driver source file only.
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This eliminates 14 warnings that were reported by the kernel test robot.
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Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
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Reported-by: kernel test robot <lkp@intel.com>
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Cc: Claudiu Beznea <claudiu.beznea@microchip.com>
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Cc: Michael Turquette <mturquette@baylibre.com>
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Cc: Stephen Boyd <sboyd@kernel.org>
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Cc: Eugen Hristev <eugen.hristev@microchip.com>
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Cc: linux-clk@vger.kernel.org
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Cc: linux-arm-kernel@lists.infradead.org
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Link: https://lore.kernel.org/r/20210819223237.20115-1-rdunlap@infradead.org
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Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/at91/sama7g5.c | 14 +++++++-------
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1 file changed, 7 insertions(+), 7 deletions(-)
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--- a/drivers/clk/at91/sama7g5.c
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+++ b/drivers/clk/at91/sama7g5.c
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@@ -35,7 +35,7 @@ static DEFINE_SPINLOCK(pmc_pll_lock);
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static DEFINE_SPINLOCK(pmc_mck0_lock);
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static DEFINE_SPINLOCK(pmc_mckX_lock);
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-/**
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+/*
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* PLL clocks identifiers
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* @PLL_ID_CPU: CPU PLL identifier
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* @PLL_ID_SYS: System PLL identifier
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@@ -56,7 +56,7 @@ enum pll_ids {
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PLL_ID_MAX,
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};
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-/**
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+/*
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* PLL type identifiers
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* @PLL_TYPE_FRAC: fractional PLL identifier
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* @PLL_TYPE_DIV: divider PLL identifier
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@@ -118,7 +118,7 @@ static const struct clk_pll_characterist
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.output = pll_outputs,
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};
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-/**
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+/*
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* PLL clocks description
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* @n: clock name
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* @p: clock parent
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@@ -285,7 +285,7 @@ static const struct {
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},
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};
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-/**
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+/*
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* Master clock (MCK[1..4]) description
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* @n: clock name
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* @ep: extra parents names array
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@@ -337,7 +337,7 @@ static const struct {
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.c = 1, },
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};
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-/**
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+/*
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* System clock description
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* @n: clock name
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* @p: clock parent name
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@@ -361,7 +361,7 @@ static const struct {
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/* Mux table for programmable clocks. */
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static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, };
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-/**
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+/*
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* Peripheral clock description
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* @n: clock name
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* @p: clock parent name
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@@ -449,7 +449,7 @@ static const struct {
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{ .n = "uhphs_clk", .p = "mck1", .id = 106, },
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};
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-/**
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+/*
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* Generic clock description
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* @n: clock name
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* @pp: PLL parents
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