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0f45601ccd
Add pending PCI patch that should correctly fix mediatek driver with Airoha SoC. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> (cherry picked from commit f22febae1a6b7c654eaf09ed02c0d0017be6d73a)
132 lines
4.6 KiB
Diff
132 lines
4.6 KiB
Diff
From 491cb9c5084790aafa02e843349492c284373231 Mon Sep 17 00:00:00 2001
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Message-ID: <491cb9c5084790aafa02e843349492c284373231.1736960708.git.lorenzo@kernel.org>
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In-Reply-To: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
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References: <0e7a622da17da0042294860cdb7a2fac091d25b1.1736960708.git.lorenzo@kernel.org>
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Thu, 9 Jan 2025 00:30:45 +0100
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Subject: [PATCH 6/6] PCI: mediatek-gen3: Avoid PCIe resetting via PERST# for
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Airoha EN7581 SoC
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Airoha EN7581 has a hw bug asserting/releasing PERST# signal causing
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occasional PCIe link down issues. In order to overcome the problem,
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PERST# signal is not asserted/released during device probe or
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suspend/resume phase and the PCIe block is reset using
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en7523_reset_assert() and en7581_pci_enable().
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Introduce flags field in the mtk_gen3_pcie_pdata struct in order to
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specify per-SoC capabilities.
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Link: https://lore.kernel.org/r/20250109-pcie-en7581-rst-fix-v4-1-4a45c89fb143@kernel.org
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Tested-by: Hui Ma <hui.ma@airoha.com>
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
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---
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drivers/pci/controller/pcie-mediatek-gen3.c | 59 ++++++++++++++-------
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1 file changed, 41 insertions(+), 18 deletions(-)
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--- a/drivers/pci/controller/pcie-mediatek-gen3.c
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+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
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@@ -127,10 +127,18 @@
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struct mtk_gen3_pcie;
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+enum mtk_gen3_pcie_flags {
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+ SKIP_PCIE_RSTB = BIT(0), /* Skip PERST# assertion during device
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+ * probing or suspend/resume phase to
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+ * avoid hw bugs/issues.
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+ */
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+};
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+
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/**
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* struct mtk_gen3_pcie_pdata - differentiate between host generations
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* @power_up: pcie power_up callback
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* @phy_resets: phy reset lines SoC data.
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+ * @flags: pcie device flags.
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*/
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struct mtk_gen3_pcie_pdata {
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int (*power_up)(struct mtk_gen3_pcie *pcie);
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@@ -138,6 +146,7 @@ struct mtk_gen3_pcie_pdata {
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const char *id[MAX_NUM_PHY_RESETS];
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int num_resets;
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} phy_resets;
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+ u32 flags;
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};
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/**
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@@ -404,22 +413,33 @@ static int mtk_pcie_startup_port(struct
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val |= PCIE_DISABLE_DVFSRC_VLT_REQ;
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writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG);
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- /* Assert all reset signals */
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- val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
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- val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
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- writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
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-
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/*
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- * Described in PCIe CEM specification sections 2.2 (PERST# Signal)
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- * and 2.2.1 (Initial Power-Up (G3 to S0)).
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- * The deassertion of PERST# should be delayed 100ms (TPVPERL)
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- * for the power and clock to become stable.
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+ * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal
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+ * causing occasional PCIe link down. In order to overcome the issue,
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+ * PCIE_RSTB signals are not asserted/released at this stage and the
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+ * PCIe block is reset using en7523_reset_assert() and
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+ * en7581_pci_enable().
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*/
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- msleep(100);
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-
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- /* De-assert reset signals */
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- val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
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- writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
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+ if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {
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+ /* Assert all reset signals */
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+ val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
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+ val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
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+ PCIE_PE_RSTB;
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+ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
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+
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+ /*
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+ * Described in PCIe CEM specification revision 6.0.
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+ *
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+ * The deassertion of PERST# should be delayed 100ms (TPVPERL)
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+ * for the power and clock to become stable.
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+ */
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+ msleep(PCIE_T_PVPERL_MS);
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+
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+ /* De-assert reset signals */
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+ val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
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+ PCIE_PE_RSTB);
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+ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
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+ }
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/* Check if the link is up or not */
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err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val,
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@@ -1178,10 +1198,12 @@ static int mtk_pcie_suspend_noirq(struct
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return err;
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}
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- /* Pull down the PERST# pin */
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- val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
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- val |= PCIE_PE_RSTB;
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- writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
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+ if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {
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+ /* Assert the PERST# pin */
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+ val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
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+ val |= PCIE_PE_RSTB;
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+ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
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+ }
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dev_dbg(pcie->dev, "entered L2 states successfully");
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@@ -1232,6 +1254,7 @@ static const struct mtk_gen3_pcie_pdata
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.id[2] = "phy-lane2",
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.num_resets = 3,
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},
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+ .flags = SKIP_PCIE_RSTB,
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};
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static const struct of_device_id mtk_pcie_of_match[] = {
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