openwrt/target/linux/realtek/dts-5.10/rtl8380_engenius_ews2910p.dts
Alexandru Gagniuc 7bba7ccde9 realtek: EnGenius EWS2910P: use the mtd3 partition for root overlay
The root overlay is mounted on the "rootfs_data" partition. This comes
at the end of the firmware image, courtesy of mtdsplit. There is very
little space left (About 1MB), which can fill up rapidly.

The "firmware" and "firmware2" partitions are part of the bootloader
dual firmware logic. They should contain independent, valid uImages.
This leaves "jffs2-cfg" (mtd3) and "jffs2-log" (mtd4) as candidates.

mtd3 is about 13.7 MB and is used by the vendor firmware to store
configuration settings. It is only erased by vendor firmware during a
factory reset. By naming this partition "rootfs_data", it becomes the
root overlay, providing significantly more room. Even with mtdsplit
wanting to create a "rootfs_data" on the firmware partition, mtd3 is
used as the overlay.

Rename "jffs2-cfg" to "rootfs_data", and profit from the extra space.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-08-13 19:19:38 +02:00

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// SPDX-License-Identifier: GPL-2.0-or-later
#include "rtl838x.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "engenius,ews2910p", "realtek,rtl838x-soc";
model = "EnGenius EWS2910P";
aliases {
led-boot = &led_power;
led-failsafe = &led_fault;
led-running = &led_power;
led-upgrade = &led_power;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x10000000>;
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
led_mode {
label = "led-mode";
gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
};
gpio1: rtl8231-gpio {
compatible = "realtek,rtl8231-gpio";
#gpio-cells = <2>;
gpio-controller;
indirect-access-bus-id = <0>;
poe_enable {
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "poe-enable";
};
sff_p9_gpios {
gpio-hog;
gpios = < 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>,
< 11 GPIO_ACTIVE_HIGH>, /* los-gpio */
< 12 GPIO_ACTIVE_LOW>; /* mod-def0-gpio */
input;
line-name = "sff-p9-gpios";
};
};
gpio-export {
compatible = "gpio-export";
sff-p9-tx-disable {
gpio-export,name = "sff-p9-tx-disable";
gpio-export,output = <1>;
gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
};
gpio-restart {
compatible = "gpio-restart";
gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
};
leds {
compatible = "gpio-leds";
led_power: led-0 {
label = "green:power";
gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
};
led_lan_mode: led-1 {
label = "green:lan-mode";
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
};
led_fault: led-2 {
label = "amber:fault";
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
};
led_poe_max: led-3 {
label = "amber:poe-max";
gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
};
};
i2c1: i2c-gpio-1 {
compatible = "i2c-gpio";
sda-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
sfp1: sfp-p10 {
compatible = "sff,sfp";
i2c-bus = <&i2c1>;
tx-disable-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
};
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
label = "u-boot-env";
reg = <0x80000 0x10000>;
read-only;
};
partition@90000 {
label = "u-boot-env2";
reg = <0x90000 0x10000>;
};
partition@a0000 {
label = "rootfs_data";
reg = <0xa0000 0xd60000>;
};
partition@e00000 {
label = "jffs2-log";
reg = <0xe00000 0x200000>;
};
partition@1000000 {
compatible = "openwrt,uimage";
label = "firmware";
reg = <0x1000000 0x800000>;
openwrt,ih-magic = <0x03802910>;
};
partition@1800000 {
label = "firmware2";
reg = <0x1800000 0x800000>;
};
};
};
};
&ethernet0 {
mdio: mdio-bus {
compatible = "realtek,rtl838x-mdio";
regmap = <&ethernet0>;
#address-cells = <1>;
#size-cells = <0>;
INTERNAL_PHY(8)
INTERNAL_PHY(9)
INTERNAL_PHY(10)
INTERNAL_PHY(11)
INTERNAL_PHY(12)
INTERNAL_PHY(13)
INTERNAL_PHY(14)
INTERNAL_PHY(15)
INTERNAL_PHY(24)
INTERNAL_PHY(26)
};
};
&switch0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT(8, 1, internal)
SWITCH_PORT(9, 2, internal)
SWITCH_PORT(10, 3, internal)
SWITCH_PORT(11, 4, internal)
SWITCH_PORT(12, 5, internal)
SWITCH_PORT(13, 6, internal)
SWITCH_PORT(14, 7, internal)
SWITCH_PORT(15, 8, internal)
SWITCH_SFP_PORT(24, 9, 1000base-x)
port@26 {
reg = <26>;
label = "lan10";
phy-mode = "1000base-x";
phy-handle = <&phy26>;
managed = "in-band-status";
sfp = <&sfp1>;
};
port@28 {
ethernet = <&ethernet0>;
reg = <28>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
&uart1 {
status = "okay";
};