mirror of
https://github.com/openwrt/openwrt.git
synced 2025-02-08 20:10:37 +00:00
7bf818c702
Deleted upstream patches:
generic:
041-genirq-affinity-Make-affinity-setting-if-activated-o.patch
ipq806x:
093-5-v5.8-ipq806x-PCI-qcom-Define-some-PARF-params-needed-for-ipq8064-SoC.patch
093-6-v5.8-ipq806x-PCI-qcom-Add-support-for-tx-term-offset-for-rev-2_1_0.patch
Merged manually:
ipq806x:
093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch
layerscape:
804-crypto-0016-MLKU-114-1-crypto-caam-reduce-page-0-regs-access-to-.patch
Build-tested: ath79/generic, ipq806x, layerscape/armv7, layerscape/armv8_64b
Run-tested: ipq806x (R7800)
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Signed-off-by: maurerr <mariusd84@gmail.com>
63 lines
2.2 KiB
Diff
63 lines
2.2 KiB
Diff
From ee367e2cdd2202b5714982739e684543cd2cee0e Mon Sep 17 00:00:00 2001
|
|
From: Ansuel Smith <ansuelsmth@gmail.com>
|
|
Date: Mon, 15 Jun 2020 23:06:00 +0200
|
|
Subject: PCI: qcom: Add missing reset for ipq806x
|
|
|
|
Add missing ext reset used by ipq8064 SoC in PCIe qcom driver.
|
|
|
|
Link: https://lore.kernel.org/r/20200615210608.21469-5-ansuelsmth@gmail.com
|
|
Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
|
|
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
|
|
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
|
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
|
Reviewed-by: Rob Herring <robh@kernel.org>
|
|
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
|
|
Cc: stable@vger.kernel.org # v4.5+
|
|
---
|
|
drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++
|
|
1 file changed, 12 insertions(+)
|
|
|
|
--- a/drivers/pci/controller/dwc/pcie-qcom.c
|
|
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
|
|
@@ -110,6 +110,7 @@ struct qcom_pcie_resources_2_1_0 {
|
|
struct reset_control *ahb_reset;
|
|
struct reset_control *por_reset;
|
|
struct reset_control *phy_reset;
|
|
+ struct reset_control *ext_reset;
|
|
struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
|
|
};
|
|
|
|
@@ -279,6 +280,10 @@ static int qcom_pcie_get_resources_2_1_0
|
|
if (IS_ERR(res->por_reset))
|
|
return PTR_ERR(res->por_reset);
|
|
|
|
+ res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext");
|
|
+ if (IS_ERR(res->ext_reset))
|
|
+ return PTR_ERR(res->ext_reset);
|
|
+
|
|
res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
|
|
return PTR_ERR_OR_ZERO(res->phy_reset);
|
|
}
|
|
@@ -292,6 +297,7 @@ static void qcom_pcie_deinit_2_1_0(struc
|
|
reset_control_assert(res->axi_reset);
|
|
reset_control_assert(res->ahb_reset);
|
|
reset_control_assert(res->por_reset);
|
|
+ reset_control_assert(res->ext_reset);
|
|
reset_control_assert(res->phy_reset);
|
|
clk_disable_unprepare(res->iface_clk);
|
|
clk_disable_unprepare(res->core_clk);
|
|
@@ -351,6 +357,12 @@ static int qcom_pcie_init_2_1_0(struct q
|
|
goto err_deassert_ahb;
|
|
}
|
|
|
|
+ ret = reset_control_deassert(res->ext_reset);
|
|
+ if (ret) {
|
|
+ dev_err(dev, "cannot deassert ext reset\n");
|
|
+ goto err_deassert_ahb;
|
|
+ }
|
|
+
|
|
/* enable PCIe clocks and resets */
|
|
val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
|
|
val &= ~BIT(0);
|