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fef6a96d9e
Allows to check cpu temperature. Huge thanks to @hnyman for valuable assistance! Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
365 lines
9.3 KiB
Diff
365 lines
9.3 KiB
Diff
From 20d4fd84bf524ad91e2cc3e4ab4020c27cfc0081 Mon Sep 17 00:00:00 2001
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From: Rajendra Nayak <rnayak@codeaurora.org>
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Date: Thu, 5 May 2016 14:21:43 +0530
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Subject: thermal: qcom: tsens-8960: Add support for 8960 family of SoCs
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8960 family of SoCs have the TSENS device as part of GCC, hence
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the driver probes the virtual child device created by GCC and
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uses the parent to extract all DT properties and reuses the GCC
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regmap.
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Also GCC/TSENS are part of a domain thats not always ON.
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Hence add .suspend and .resume hooks to save and restore some of
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the inited register context.
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Also 8960 family have some of the TSENS init sequence thats
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required to be done by the HLOS driver (some later versions of TSENS
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do not export these registers to non-secure world, and hence need
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these initializations to be done by secure bootloaders)
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8660 from the same family has just one sensor and hence some register
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offset/layout differences which need special handling in the driver.
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Based on the original code from Siddartha Mohanadoss, Stephen Boyd and
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Narendran Rajan.
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Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
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Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
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Signed-off-by: Zhang Rui <rui.zhang@intel.com>
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---
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drivers/thermal/qcom/Makefile | 2 +-
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drivers/thermal/qcom/tsens-8960.c | 292 ++++++++++++++++++++++++++++++++++++++
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drivers/thermal/qcom/tsens.c | 8 +-
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drivers/thermal/qcom/tsens.h | 2 +-
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4 files changed, 298 insertions(+), 6 deletions(-)
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create mode 100644 drivers/thermal/qcom/tsens-8960.c
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--- a/drivers/thermal/qcom/Makefile
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+++ b/drivers/thermal/qcom/Makefile
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@@ -1,2 +1,2 @@
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obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o
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-qcom_tsens-y += tsens.o tsens-common.o tsens-8916.o tsens-8974.o
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+qcom_tsens-y += tsens.o tsens-common.o tsens-8916.o tsens-8974.o tsens-8960.o
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--- /dev/null
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+++ b/drivers/thermal/qcom/tsens-8960.c
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@@ -0,0 +1,292 @@
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+/*
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+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 and
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+ * only version 2 as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ */
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+
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+#include <linux/platform_device.h>
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+#include <linux/delay.h>
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+#include <linux/bitops.h>
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+#include <linux/regmap.h>
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+#include <linux/thermal.h>
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+#include "tsens.h"
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+
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+#define CAL_MDEGC 30000
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+
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+#define CONFIG_ADDR 0x3640
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+#define CONFIG_ADDR_8660 0x3620
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+/* CONFIG_ADDR bitmasks */
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+#define CONFIG 0x9b
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+#define CONFIG_MASK 0xf
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+#define CONFIG_8660 1
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+#define CONFIG_SHIFT_8660 28
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+#define CONFIG_MASK_8660 (3 << CONFIG_SHIFT_8660)
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+
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+#define STATUS_CNTL_ADDR_8064 0x3660
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+#define CNTL_ADDR 0x3620
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+/* CNTL_ADDR bitmasks */
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+#define EN BIT(0)
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+#define SW_RST BIT(1)
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+#define SENSOR0_EN BIT(3)
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+#define SLP_CLK_ENA BIT(26)
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+#define SLP_CLK_ENA_8660 BIT(24)
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+#define MEASURE_PERIOD 1
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+#define SENSOR0_SHIFT 3
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+
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+/* INT_STATUS_ADDR bitmasks */
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+#define MIN_STATUS_MASK BIT(0)
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+#define LOWER_STATUS_CLR BIT(1)
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+#define UPPER_STATUS_CLR BIT(2)
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+#define MAX_STATUS_MASK BIT(3)
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+
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+#define THRESHOLD_ADDR 0x3624
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+/* THRESHOLD_ADDR bitmasks */
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+#define THRESHOLD_MAX_LIMIT_SHIFT 24
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+#define THRESHOLD_MIN_LIMIT_SHIFT 16
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+#define THRESHOLD_UPPER_LIMIT_SHIFT 8
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+#define THRESHOLD_LOWER_LIMIT_SHIFT 0
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+
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+/* Initial temperature threshold values */
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+#define LOWER_LIMIT_TH 0x50
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+#define UPPER_LIMIT_TH 0xdf
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+#define MIN_LIMIT_TH 0x0
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+#define MAX_LIMIT_TH 0xff
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+
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+#define S0_STATUS_ADDR 0x3628
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+#define INT_STATUS_ADDR 0x363c
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+#define TRDY_MASK BIT(7)
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+#define TIMEOUT_US 100
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+
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+static int suspend_8960(struct tsens_device *tmdev)
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+{
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+ int ret;
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+ unsigned int mask;
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+ struct regmap *map = tmdev->map;
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+
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+ ret = regmap_read(map, THRESHOLD_ADDR, &tmdev->ctx.threshold);
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+ if (ret)
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+ return ret;
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+
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+ ret = regmap_read(map, CNTL_ADDR, &tmdev->ctx.control);
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+ if (ret)
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+ return ret;
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+
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+ if (tmdev->num_sensors > 1)
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+ mask = SLP_CLK_ENA | EN;
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+ else
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+ mask = SLP_CLK_ENA_8660 | EN;
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+
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+ ret = regmap_update_bits(map, CNTL_ADDR, mask, 0);
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+ if (ret)
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+ return ret;
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+
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+ return 0;
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+}
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+
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+static int resume_8960(struct tsens_device *tmdev)
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+{
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+ int ret;
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+ struct regmap *map = tmdev->map;
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+
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+ ret = regmap_update_bits(map, CNTL_ADDR, SW_RST, SW_RST);
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+ if (ret)
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+ return ret;
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+
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+ /*
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+ * Separate CONFIG restore is not needed only for 8660 as
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+ * config is part of CTRL Addr and its restored as such
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+ */
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+ if (tmdev->num_sensors > 1) {
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+ ret = regmap_update_bits(map, CONFIG_ADDR, CONFIG_MASK, CONFIG);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ ret = regmap_write(map, THRESHOLD_ADDR, tmdev->ctx.threshold);
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+ if (ret)
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+ return ret;
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+
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+ ret = regmap_write(map, CNTL_ADDR, tmdev->ctx.control);
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+ if (ret)
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+ return ret;
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+
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+ return 0;
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+}
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+
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+static int enable_8960(struct tsens_device *tmdev, int id)
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+{
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+ int ret;
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+ u32 reg, mask;
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+
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+ ret = regmap_read(tmdev->map, CNTL_ADDR, ®);
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+ if (ret)
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+ return ret;
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+
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+ mask = BIT(id + SENSOR0_SHIFT);
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+ ret = regmap_write(tmdev->map, CNTL_ADDR, reg | SW_RST);
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+ if (ret)
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+ return ret;
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+
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+ if (tmdev->num_sensors > 1)
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+ reg |= mask | SLP_CLK_ENA | EN;
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+ else
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+ reg |= mask | SLP_CLK_ENA_8660 | EN;
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+
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+ ret = regmap_write(tmdev->map, CNTL_ADDR, reg);
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+ if (ret)
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+ return ret;
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+
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+ return 0;
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+}
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+
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+static void disable_8960(struct tsens_device *tmdev)
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+{
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+ int ret;
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+ u32 reg_cntl;
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+ u32 mask;
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+
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+ mask = GENMASK(tmdev->num_sensors - 1, 0);
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+ mask <<= SENSOR0_SHIFT;
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+ mask |= EN;
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+
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+ ret = regmap_read(tmdev->map, CNTL_ADDR, ®_cntl);
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+ if (ret)
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+ return;
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+
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+ reg_cntl &= ~mask;
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+
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+ if (tmdev->num_sensors > 1)
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+ reg_cntl &= ~SLP_CLK_ENA;
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+ else
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+ reg_cntl &= ~SLP_CLK_ENA_8660;
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+
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+ regmap_write(tmdev->map, CNTL_ADDR, reg_cntl);
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+}
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+
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+static int init_8960(struct tsens_device *tmdev)
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+{
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+ int ret, i;
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+ u32 reg_cntl;
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+
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+ tmdev->map = dev_get_regmap(tmdev->dev, NULL);
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+ if (!tmdev->map)
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+ return -ENODEV;
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+
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+ /*
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+ * The status registers for each sensor are discontiguous
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+ * because some SoCs have 5 sensors while others have more
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+ * but the control registers stay in the same place, i.e
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+ * directly after the first 5 status registers.
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+ */
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+ for (i = 0; i < tmdev->num_sensors; i++) {
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+ if (i >= 5)
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+ tmdev->sensor[i].status = S0_STATUS_ADDR + 40;
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+ tmdev->sensor[i].status += i * 4;
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+ }
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+
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+ reg_cntl = SW_RST;
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+ ret = regmap_update_bits(tmdev->map, CNTL_ADDR, SW_RST, reg_cntl);
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+ if (ret)
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+ return ret;
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+
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+ if (tmdev->num_sensors > 1) {
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+ reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18);
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+ reg_cntl &= ~SW_RST;
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+ ret = regmap_update_bits(tmdev->map, CONFIG_ADDR,
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+ CONFIG_MASK, CONFIG);
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+ } else {
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+ reg_cntl |= SLP_CLK_ENA_8660 | (MEASURE_PERIOD << 16);
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+ reg_cntl &= ~CONFIG_MASK_8660;
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+ reg_cntl |= CONFIG_8660 << CONFIG_SHIFT_8660;
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+ }
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+
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+ reg_cntl |= GENMASK(tmdev->num_sensors - 1, 0) << SENSOR0_SHIFT;
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+ ret = regmap_write(tmdev->map, CNTL_ADDR, reg_cntl);
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+ if (ret)
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+ return ret;
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+
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+ reg_cntl |= EN;
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+ ret = regmap_write(tmdev->map, CNTL_ADDR, reg_cntl);
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+ if (ret)
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+ return ret;
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+
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+ return 0;
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+}
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+
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+static int calibrate_8960(struct tsens_device *tmdev)
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+{
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+ int i;
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+ char *data;
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+
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+ ssize_t num_read = tmdev->num_sensors;
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+ struct tsens_sensor *s = tmdev->sensor;
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+
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+ data = qfprom_read(tmdev->dev, "calib");
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+ if (IS_ERR(data))
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+ data = qfprom_read(tmdev->dev, "calib_backup");
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+ if (IS_ERR(data))
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+ return PTR_ERR(data);
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+
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+ for (i = 0; i < num_read; i++, s++)
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+ s->offset = data[i];
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+
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+ return 0;
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+}
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+
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+/* Temperature on y axis and ADC-code on x-axis */
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+static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s)
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+{
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+ int slope, offset;
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+
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+ slope = thermal_zone_get_slope(s->tzd);
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+ offset = CAL_MDEGC - slope * s->offset;
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+
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+ return adc_code * slope + offset;
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+}
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+
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+static int get_temp_8960(struct tsens_device *tmdev, int id, int *temp)
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+{
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+ int ret;
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+ u32 code, trdy;
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+ const struct tsens_sensor *s = &tmdev->sensor[id];
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+ unsigned long timeout;
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+
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+ timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
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+ do {
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+ ret = regmap_read(tmdev->map, INT_STATUS_ADDR, &trdy);
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+ if (ret)
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+ return ret;
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+ if (!(trdy & TRDY_MASK))
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+ continue;
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+ ret = regmap_read(tmdev->map, s->status, &code);
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+ if (ret)
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+ return ret;
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+ *temp = code_to_mdegC(code, s);
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+ return 0;
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+ } while (time_before(jiffies, timeout));
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+
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+ return -ETIMEDOUT;
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+}
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+
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+const struct tsens_ops ops_8960 = {
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+ .init = init_8960,
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+ .calibrate = calibrate_8960,
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+ .get_temp = get_temp_8960,
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+ .enable = enable_8960,
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+ .disable = disable_8960,
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+ .suspend = suspend_8960,
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+ .resume = resume_8960,
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+};
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+
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+const struct tsens_data data_8960 = {
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+ .num_sensors = 11,
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+ .ops = &ops_8960,
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+};
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--- a/drivers/thermal/qcom/tsens.c
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+++ b/drivers/thermal/qcom/tsens.c
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@@ -122,10 +122,10 @@ static int tsens_probe(struct platform_d
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np = dev->of_node;
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id = of_match_node(tsens_table, np);
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- if (!id)
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- return -EINVAL;
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-
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- data = id->data;
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+ if (id)
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+ data = id->data;
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+ else
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+ data = &data_8960;
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if (data->num_sensors <= 0) {
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dev_err(dev, "invalid number of sensors\n");
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--- a/drivers/thermal/qcom/tsens.h
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+++ b/drivers/thermal/qcom/tsens.h
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@@ -87,6 +87,6 @@ void compute_intercept_slope(struct tsen
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int init_common(struct tsens_device *);
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int get_temp_common(struct tsens_device *, int, int *);
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-extern const struct tsens_data data_8916, data_8974;
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+extern const struct tsens_data data_8916, data_8974, data_8960;
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#endif /* __QCOM_TSENS_H__ */
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