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63066d3006
Reworked: - 0034 patchset update Added: - 080 Add support for pinctrl-msm framework Removed: - 0074-ipq806x-usb-Control-USB-master-reset.patch (we now have a dedicated driver for qcom usb) - 0047-mtd-nand-Create-a-BBT-flag-to-access-bad-block-marke (merged upstream) - 310-msm-adhoc-bus-support (it looks like it was never actually used in any dts) Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> [commit subject and description facelift, SoB fix] Signed-off-by: Petr Štetiar <ynezz@true.cz>
100 lines
3.1 KiB
Diff
100 lines
3.1 KiB
Diff
From 40e5ddf4f84869815129551f4a8cfc2c223ebeae Mon Sep 17 00:00:00 2001
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From: Stephen Boyd <sboyd@codeaurora.org>
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Date: Tue, 14 Aug 2018 17:42:28 +0530
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Subject: [PATCH 09/12] dt-bindings: arm: Document qcom,kpss-gcc
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The ACC and GCC regions present in KPSSv1 contain registers to
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control clocks and power to each Krait CPU and L2. Documenting
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the bindings here.
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Reviewed-by: Rob Herring <robh@kernel.org>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Signed-off-by: Sricharan R <sricharan@codeaurora.org>
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Tested-by: Craig Tatlor <ctatlor97@gmail.com>
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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.../bindings/arm/msm/qcom,kpss-acc.txt | 19 ++++++++
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.../bindings/arm/msm/qcom,kpss-gcc.txt | 44 +++++++++++++++++++
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2 files changed, 63 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
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--- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
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+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
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@@ -21,10 +21,29 @@ PROPERTIES
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the register region. An optional second element specifies
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the base address and size of the alias register region.
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+- clocks:
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+ Usage: required
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+ Value type: <prop-encoded-array>
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+ Definition: reference to the pll parents.
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+
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+- clock-names:
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+ Usage: required
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+ Value type: <stringlist>
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+ Definition: must be "pll8_vote", "pxo".
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+
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+- clock-output-names:
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+ Usage: optional
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+ Value type: <string>
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+ Definition: Name of the output clock. Typically acpuX_aux where X is a
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+ CPU number starting at 0.
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+
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Example:
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clock-controller@2088000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0x02088000 0x1000>,
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<0x02008000 0x1000>;
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+ clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
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+ clock-names = "pll8_vote", "pxo";
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+ clock-output-names = "acpu0_aux";
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};
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
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@@ -0,0 +1,44 @@
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+Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
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+
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+PROPERTIES
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+
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+- compatible:
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+ Usage: required
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+ Value type: <string>
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+ Definition: should be one of the following. The generic compatible
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+ "qcom,kpss-gcc" should also be included.
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+ "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
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+ "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
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+ "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
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+ "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
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+
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+- reg:
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+ Usage: required
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+ Value type: <prop-encoded-array>
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+ Definition: base address and size of the register region
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+
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+- clocks:
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+ Usage: required
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+ Value type: <prop-encoded-array>
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+ Definition: reference to the pll parents.
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+
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+- clock-names:
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+ Usage: required
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+ Value type: <stringlist>
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+ Definition: must be "pll8_vote", "pxo".
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+
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+- clock-output-names:
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+ Usage: required
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+ Value type: <string>
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+ Definition: Name of the output clock. Typically acpu_l2_aux indicating
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+ an L2 cache auxiliary clock.
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+
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+Example:
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+
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+ l2cc: clock-controller@2011000 {
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+ compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
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+ reg = <0x2011000 0x1000>;
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+ clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
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+ clock-names = "pll8_vote", "pxo";
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+ clock-output-names = "acpu_l2_aux";
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+ };
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