openwrt/target/linux/d1/patches-6.1/0097-drm-sun4i-dsi-Add-the-A100-variant.patch
Zoltan HERPAI 99545b4bb1 d1: add new target
This target adds support for the Allwinner D1 RISC-V based SoCs.

 - RISC-V single-core T-Head C906 (RV64GCV)
 - Tensilica HiFi4 DSP
 - DDR2/DDR3 support
 - 10/100/1000M ethernet
 - usual peripherals like USB2, SPI, I2C, PWM, etc.

Four boards are supported:
 - Dongshan Nezha STU
    - 512Mb RAM
    - ethernet

 - LicheePi RV Dock
    - 512Mb RAM
    - wireless-only (RTL8723DS)

 - MangoPi MQ-Pro
    - 512Mb RAM
    - there are pads available for an SPI flash
    - wireless-only (RTL8723DS)

 - Nezha D1
    - 512Mb/1Gb/2Gb RAM
    - 256Mb NAND flash
    - ethernet, wireless

Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.

Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
2024-02-29 16:50:22 +01:00

67 lines
2.4 KiB
Diff

From 713029c6a33df9218d11593bc5be79420715633f Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 7 Aug 2022 11:06:22 -0500
Subject: [PATCH 097/117] drm/sun4i: dsi: Add the A100 variant
The A100 variant of the MIPI DSI controller now gets its module clock
from the TCON via the TCON TOP, so the clock rate cannot be set to a
fixed value. Otherwise, it appears to be the same as the A31 variant.
Cover-letter:
drm/sun4i: dsi: Support the A100/D1 controller variant
This series adds support for the digital part of the DSI controller
found in the A100 and D1 SoCs (plus T7, which is not supported by
mainline Linux). There are two changes to the hardware integration:
1) the module clock routes through the TCON TOP, and
2) the separate I/O domain is removed.
The actual register interface appears to be the same as before. The
register definitions in the D1 BSP exactly match the A64 BSP.
The BSP describes this as the "40nm" DSI controller variant. There is
also a "28nm" variant with a different register interface; that one is
found in a different subset of SoCs (V5 and A50).
A100/D1 also come with an updated DPHY, described by the BSP as a
"combo" PHY, which is now also used for LVDS channel 0. (LVDS and DSI
share the same pins on Port D.) Since that is a different subsystem,
I am sending that as a separate series.
END
Series-to: Chen-Yu Tsai <wens@csie.org>
Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
Series-to: Maxime Ripard <mripard@kernel.org>
Series-version: 2
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -1223,6 +1223,10 @@ static const struct sun6i_dsi_variant su
static const struct sun6i_dsi_variant sun50i_a64_mipi_dsi_variant = {
};
+static const struct sun6i_dsi_variant sun50i_a100_mipi_dsi_variant = {
+ .has_mod_clk = true,
+};
+
static const struct of_device_id sun6i_dsi_of_table[] = {
{
.compatible = "allwinner,sun6i-a31-mipi-dsi",
@@ -1232,6 +1236,10 @@ static const struct of_device_id sun6i_d
.compatible = "allwinner,sun50i-a64-mipi-dsi",
.data = &sun50i_a64_mipi_dsi_variant,
},
+ {
+ .compatible = "allwinner,sun50i-a100-mipi-dsi",
+ .data = &sun50i_a100_mipi_dsi_variant,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);