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133 lines
4.3 KiB
Diff
133 lines
4.3 KiB
Diff
From: Rabeeh Khoury <rabeeh@marvell.com>
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Date: Sun, 22 Mar 2009 15:30:32 +0000 (+0200)
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Subject: [ARM] Kirkwood: peripherals clock gating for power management
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X-Git-Url: http://git.marvell.com/?p=orion.git;a=commitdiff_plain;h=c0c3df02efed0e5dea9aa4d8313e06e1f68f2cb4;hp=039b97666e1335eac517c7d35a0fa1143af689f0
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[ARM] Kirkwood: peripherals clock gating for power management
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1. Enabling clock gating of unused peripherals
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2. PLL and PHY of the units are also disabled (when possible.
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Signed-off-by: Rabeeh Khoury <rabeeh@marvell.com>
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[ This needs to be revisited to make power handling dynamic and per device. -- Nico ]
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---
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--- a/arch/arm/mach-kirkwood/common.c
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+++ b/arch/arm/mach-kirkwood/common.c
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@@ -786,6 +786,38 @@ static void __init kirkwood_l2_init(void
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#endif
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}
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+void __init kirkwood_clock_gate(u32 reg)
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+{
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+ printk(KERN_INFO "Kirkwood: Gating clock using mask 0x%x\n", reg);
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+ /* First make sure that the units are accessible */
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+ writel(readl(CLOCK_GATING_CTRL) | reg, CLOCK_GATING_CTRL);
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+ /* For SATA first shutdown the phy */
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+ if (reg & CGC_SATA0) {
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+ /* Disable PLL and IVREF */
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+ writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
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+ /* Disable PHY */
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+ writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
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+ }
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+ if (reg & CGC_SATA1) {
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+ /* Disable PLL and IVREF */
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+ writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
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+ /* Disable PHY */
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+ writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
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+ }
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+ /* For PCI-E first shutdown the phy */
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+ if (reg & CGC_PEX0) {
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+ writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
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+ while (1) {
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+ if (readl(PCIE_STATUS) & 0x1)
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+ break;
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+ }
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+ writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
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+ }
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+ /* Now gate clock the required units */
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+ writel(readl(CLOCK_GATING_CTRL) & ~reg, CLOCK_GATING_CTRL);
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+ return;
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+}
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+
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void __init kirkwood_init(void)
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{
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printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
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--- a/arch/arm/mach-kirkwood/common.h
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+++ b/arch/arm/mach-kirkwood/common.h
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@@ -22,6 +22,7 @@ struct mvsdio_platform_data;
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void kirkwood_map_io(void);
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void kirkwood_init(void);
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void kirkwood_init_irq(void);
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+void __init kirkwood_clock_gate(u32 reg);
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extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
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void kirkwood_setup_cpu_mbus(void);
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--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
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+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
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@@ -39,4 +39,20 @@
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#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128)
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#define L2_WRITETHROUGH 0x00000010
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+#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c)
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+#define CGC_GE0 0x1
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+#define CGC_PEX0 0x4
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+#define CGC_USB0 0x8
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+#define CGC_SDIO 0x10
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+#define CGC_TSU 0x20
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+#define CGC_NAND_SPI 0x80
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+#define CGC_XOR0 0x100
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+#define CGC_AUDIO 0x200
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+#define CGC_SATA0 0x4000
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+#define CGC_SATA1 0x8000
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+#define CGC_XOR1 0x10000
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+#define CGC_CRYPTO 0x20000
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+#define CGC_GE1 0x80000
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+#define CGC_TDM 0x100000
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+
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#endif
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--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
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+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
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@@ -64,6 +64,8 @@
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#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
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#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
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+#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70)
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+#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04)
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#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
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@@ -80,6 +82,11 @@
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#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
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#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
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+#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x80000)
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+#define SATA0_IF_CTRL (SATA_VIRT_BASE | 0x2050)
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+#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE | 0x2330)
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+#define SATA1_IF_CTRL (SATA_VIRT_BASE | 0x4050)
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+#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE | 0x4330)
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#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
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--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
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+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
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@@ -19,6 +19,7 @@
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <mach/kirkwood.h>
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+#include <mach/bridge-regs.h>
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#include <plat/mvsdio.h>
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#include <plat/orion_nand.h>
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#include "common.h"
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@@ -122,6 +123,8 @@ static void __init sheevaplug_init(void)
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platform_device_register(&sheevaplug_nand_flash);
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platform_device_register(&sheevaplug_leds);
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+ kirkwood_clock_gate(CGC_PEX0 | CGC_TSU | CGC_AUDIO | CGC_SATA0 |\
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+ CGC_SATA1 | CGC_CRYPTO | CGC_GE1 | CGC_TDM);
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}
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MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board")
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