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67 lines
1.7 KiB
Diff
67 lines
1.7 KiB
Diff
From 4d805af8246efdc330d6af9a8bd10ce892327598 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 24 Jan 2014 17:01:17 +0100
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Subject: [PATCH 03/53] MIPS: ralink: cleanup early_printk
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Add support for the new MT7621/8 SoC and kill ifdefs.
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Cleanup some whitespace error while we are at it.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/ralink/early_printk.c | 25 +++++++++++++++++++++++++
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1 file changed, 25 insertions(+)
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diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c
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index 255d695..c04ee53 100644
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--- a/arch/mips/ralink/early_printk.c
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+++ b/arch/mips/ralink/early_printk.c
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@@ -25,11 +25,13 @@
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#define MT7628_CHIP_NAME1 0x20203832
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#define UART_REG_TX 0x04
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+#define UART_REG_LCR 0x0c
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#define UART_REG_LSR 0x14
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#define UART_REG_LSR_RT2880 0x1c
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static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE);
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static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE);
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+static int init_complete;
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static inline void uart_w32(u32 val, unsigned reg)
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{
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@@ -47,8 +49,31 @@ static inline int soc_is_mt7628(void)
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(__raw_readl(chipid_membase) == MT7628_CHIP_NAME1);
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}
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+static inline void find_uart_base(void)
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+{
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+ int i;
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+
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+ if (!soc_is_mt7628())
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+ return;
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+
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+ for (i = 0; i < 3; i++) {
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+ u32 reg = uart_r32(UART_REG_LCR + (0x100 * i));
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+
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+ if (!reg)
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+ continue;
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+
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+ uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE + (0x100 * i));
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+ break;
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+ }
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+}
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+
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void prom_putchar(unsigned char ch)
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{
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+ if (!init_complete) {
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+ find_uart_base();
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+ init_complete = 1;
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+ }
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+
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if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) {
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uart_w32(ch, UART_TX);
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while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
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--
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1.7.10.4
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