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f02f6aaa8d
Currently, ipq807x only covers Qualcomm IPQ807x SoC-s. However, Qualcomm also has IPQ60xx and IPQ50xx SoC-s under the AX WiSoC-s and they share a lot of stuff with IPQ807x, especially IPQ60xx so to avoid duplicating kernel patches and everything lets make a common target with per SoC subtargets. Start doing that by renaming ipq807x to qualcommax so that dependencies on ipq807x target can be updated. Signed-off-by: Robert Marko <robimarko@gmail.com>
131 lines
3.0 KiB
Diff
131 lines
3.0 KiB
Diff
From c3cc0c2a17f552be2426200e47a9e2c62cf449ce Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Fri, 19 Aug 2022 00:02:45 +0200
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Subject: [PATCH] arm64: dts: qcom: ipq8074: add thermal nodes
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IPQ8074 has a tsens v2.3.0 peripheral which monitors
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temperatures around the various subsystems on the
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die.
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So lets add the tsens and thermal zone nodes, passive
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CPU cooling will come in later patches after CPU frequency
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scaling is supported.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20220818220245.338396-5-robimarko@gmail.com
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++
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1 file changed, 96 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -274,6 +274,16 @@
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status = "disabled";
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};
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+ tsens: thermal-sensor@4a9000 {
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+ compatible = "qcom,ipq8074-tsens";
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+ reg = <0x4a9000 0x1000>, /* TM */
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+ <0x4a8000 0x1000>; /* SROT */
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+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "combined";
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+ #qcom,sensors = <16>;
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+ #thermal-sensor-cells = <1>;
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+ };
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+
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cryptobam: dma-controller@704000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x00704000 0x20000>;
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@@ -874,4 +884,90 @@
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<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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+
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+ thermal-zones {
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+ nss-top-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 4>;
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+ };
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+
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+ nss0-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 5>;
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+ };
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+
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+ nss1-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 6>;
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+ };
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+
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+ wcss-phya0-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 7>;
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+ };
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+
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+ wcss-phya1-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 8>;
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+ };
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+
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+ cpu0_thermal: cpu0-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 9>;
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+ };
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+
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+ cpu1_thermal: cpu1-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 10>;
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+ };
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+
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+ cpu2_thermal: cpu2-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 11>;
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+ };
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+
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+ cpu3_thermal: cpu3-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 12>;
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+ };
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+
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+ cluster_thermal: cluster-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 13>;
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+ };
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+
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+ wcss-phyb0-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 14>;
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+ };
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+
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+ wcss-phyb1-thermal {
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+ polling-delay-passive = <250>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsens 15>;
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+ };
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+ };
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};
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