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https://github.com/openwrt/openwrt.git
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e7aa4c0db7
Refactor pcie-oxnas to have shared resources in syscon and new pcie-phy driver. Hopefully this revives PCIe... Signed-off-by: Daniel Golle <daniel@makrotopia.org>
115 lines
3.5 KiB
Diff
115 lines
3.5 KiB
Diff
--- a/drivers/pci/host/Kconfig
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+++ b/drivers/pci/host/Kconfig
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@@ -220,4 +220,9 @@ config VMD
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To compile this driver as a module, choose M here: the
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module will be called vmd.
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+config PCIE_OXNAS
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+ bool "PLX Oxnas PCIe controller"
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+ depends on ARCH_OXNAS
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+ select PCIEPORTBUS
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+
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endmenu
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--- a/drivers/pci/host/Makefile
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+++ b/drivers/pci/host/Makefile
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@@ -20,6 +20,7 @@ obj-$(CONFIG_PCIE_ALTERA) += pcie-altera
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obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
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obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
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obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
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+obj-$(CONFIG_PCIE_OXNAS) += pcie-oxnas.o
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obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
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obj-$(CONFIG_VMD) += vmd.o
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--- a/arch/arm/boot/dts/ox820.dtsi
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+++ b/arch/arm/boot/dts/ox820.dtsi
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@@ -316,6 +316,89 @@
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reg = <0x1000 0x1000>,
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<0x100 0x500>;
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};
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+
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+ pcie0: pcie-controller@c00000 {
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+ compatible = "plxtech,nas782x-pcie";
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+ device_type = "pci";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ /* flag & space bus address host address size */
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+ ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000
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+ 0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000
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+ 0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000
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+ 0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>;
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+
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+ bus-range = <0x00 0x7f>;
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+
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+ /* cfg inbound translator */
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+ reg = <0x0 0x1000>, <0x100000 0x100>;
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+
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+ phys = <&pcie_phy>;
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+ phy-names = "pcie-phy";
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+
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+ #interrupt-cells = <1>;
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+ /* wild card mask, match all bus address & interrupt specifier */
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+ /* format: bus address mask, interrupt specifier mask */
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+ /* each bit 1 means need match, 0 means ignored when match */
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+ interrupt-map-mask = <0 0 0 0>;
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+ /* format: a list of: bus address, interrupt specifier,
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+ * parent interrupt controller & specifier */
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+ interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
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+
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+ gpios = <&gpio1 12 0>;
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+ clocks = <&stdclk CLK_820_PCIEA>, <&pllb>;
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+ clock-names = "pcie", "busclk";
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+ resets = <&reset RESET_PCIEA>;
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+ reset-names = "pcie";
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+
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+ plxtech,pcie-hcsl-bit = <2>;
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+ plxtech,pcie-ctrl-offset = <0x120>;
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+ plxtech,pcie-outbound-offset = <0x138>;
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+ status = "disabled";
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+ };
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+
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+ pcie1: pcie-controller@e00000 {
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+ compatible = "plxtech,nas782x-pcie";
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+ device_type = "pci";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ /* flag & space bus address host address size */
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+ ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000
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+ 0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000
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+ 0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000
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+ 0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>;
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+
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+ bus-range = <0x80 0xff>;
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+
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+ /* cfg inbound translator */
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+ reg = <0x0 0x1000>, <0x100000 0x100>;
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+
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+ phys = <&pcie_phy>;
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+ phy-names = "pcie-phy";
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+
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+ #interrupt-cells = <1>;
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+ /* wild card mask, match all bus address & interrupt specifier */
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+ /* format: bus address mask, interrupt specifier mask */
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+ /* each bit 1 means need match, 0 means ignored when match */
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+ interrupt-map-mask = <0 0 0 0>;
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+ /* format: a list of: bus address, interrupt specifier,
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+ * parent interrupt controller & specifier */
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+ interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
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+
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+ /* gpios = <&gpio1 12 0>; */
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+ clocks = <&stdclk CLK_820_PCIEB>, <&pllb>;
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+ clock-names = "pcie", "busclk";
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+ resets = <&reset RESET_PCIEB>;
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+ reset-names = "pcie";
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+
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+ plxtech,pcie-hcsl-bit = <3>;
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+ plxtech,pcie-ctrl-offset = <0x124>;
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+ plxtech,pcie-outbound-offset = <0x174>;
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+ status = "disabled";
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+ };
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+
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};
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};
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};
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