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0a51f13145
The backported patch is broken, since kernel 6.1 has not
'include/linux/firmware' directory yet.
Fix the include to the correct path.
Fixes: #14115
Fixes: 52c365f055 ("kernel: backport v6.6 nvmem changes")
Signed-off-by: Andrey VOLKOV <andrey@volkov.fr>
[ improve commit description and title ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
153 lines
4.4 KiB
Diff
153 lines
4.4 KiB
Diff
From 0a9ec38c47c1ca4528aa058e2b9ea61901a7e632 Mon Sep 17 00:00:00 2001
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From: Komal Bajaj <quic_kbajaj@quicinc.com>
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Date: Tue, 1 Aug 2023 12:10:25 +0530
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Subject: [PATCH] nvmem: sec-qfprom: Add Qualcomm secure QFPROM support
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For some of the Qualcomm SoC's, it is possible that
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some of the fuse regions or entire qfprom region is
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protected from non-secure access. In such situations,
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the OS will have to use secure calls to read the region.
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With that motivation, add secure qfprom driver.
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Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
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Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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---
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drivers/nvmem/Kconfig | 13 ++++++
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drivers/nvmem/Makefile | 2 +
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drivers/nvmem/sec-qfprom.c | 96 ++++++++++++++++++++++++++++++++++++++
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3 files changed, 111 insertions(+)
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create mode 100644 drivers/nvmem/sec-qfprom.c
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--- a/drivers/nvmem/Kconfig
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+++ b/drivers/nvmem/Kconfig
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@@ -226,6 +226,19 @@ config NVMEM_QCOM_QFPROM
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This driver can also be built as a module. If so, the module
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will be called nvmem_qfprom.
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+config NVMEM_QCOM_SEC_QFPROM
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+ tristate "QCOM SECURE QFPROM Support"
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+ depends on ARCH_QCOM || COMPILE_TEST
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+ depends on HAS_IOMEM
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+ depends on OF
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+ select QCOM_SCM
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+ help
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+ Say y here to enable secure QFPROM support. The secure QFPROM provides access
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+ functions for QFPROM data to rest of the drivers via nvmem interface.
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+
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+ This driver can also be built as a module. If so, the module will be called
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+ nvmem_sec_qfprom.
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+
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config NVMEM_RAVE_SP_EEPROM
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tristate "Rave SP EEPROM Support"
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depends on RAVE_SP_CORE
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--- a/drivers/nvmem/Makefile
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+++ b/drivers/nvmem/Makefile
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@@ -46,6 +46,8 @@ obj-$(CONFIG_NVMEM_NINTENDO_OTP) += nvme
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nvmem-nintendo-otp-y := nintendo-otp.o
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obj-$(CONFIG_NVMEM_QCOM_QFPROM) += nvmem_qfprom.o
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nvmem_qfprom-y := qfprom.o
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+obj-$(CONFIG_NVMEM_QCOM_SEC_QFPROM) += nvmem_sec_qfprom.o
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+nvmem_sec_qfprom-y := sec-qfprom.o
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obj-$(CONFIG_NVMEM_RAVE_SP_EEPROM) += nvmem-rave-sp-eeprom.o
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nvmem-rave-sp-eeprom-y := rave-sp-eeprom.o
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obj-$(CONFIG_NVMEM_RMEM) += nvmem-rmem.o
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--- /dev/null
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+++ b/drivers/nvmem/sec-qfprom.c
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@@ -0,0 +1,96 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+/*
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+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+#include <linux/qcom_scm.h>
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+#include <linux/mod_devicetable.h>
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+#include <linux/nvmem-provider.h>
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+#include <linux/platform_device.h>
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+#include <linux/pm_runtime.h>
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+
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+/**
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+ * struct sec_qfprom - structure holding secure qfprom attributes
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+ *
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+ * @base: starting physical address for secure qfprom corrected address space.
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+ * @dev: qfprom device structure.
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+ */
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+struct sec_qfprom {
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+ phys_addr_t base;
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+ struct device *dev;
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+};
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+
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+static int sec_qfprom_reg_read(void *context, unsigned int reg, void *_val, size_t bytes)
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+{
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+ struct sec_qfprom *priv = context;
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+ unsigned int i;
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+ u8 *val = _val;
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+ u32 read_val;
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+ u8 *tmp;
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+
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+ for (i = 0; i < bytes; i++, reg++) {
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+ if (i == 0 || reg % 4 == 0) {
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+ if (qcom_scm_io_readl(priv->base + (reg & ~3), &read_val)) {
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+ dev_err(priv->dev, "Couldn't access fuse register\n");
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+ return -EINVAL;
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+ }
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+ tmp = (u8 *)&read_val;
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+ }
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+
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+ val[i] = tmp[reg & 3];
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+ }
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+
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+ return 0;
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+}
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+
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+static int sec_qfprom_probe(struct platform_device *pdev)
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+{
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+ struct nvmem_config econfig = {
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+ .name = "sec-qfprom",
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+ .stride = 1,
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+ .word_size = 1,
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+ .id = NVMEM_DEVID_AUTO,
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+ .reg_read = sec_qfprom_reg_read,
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+ };
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+ struct device *dev = &pdev->dev;
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+ struct nvmem_device *nvmem;
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+ struct sec_qfprom *priv;
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+ struct resource *res;
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+
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+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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+ if (!priv)
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+ return -ENOMEM;
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ if (!res)
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+ return -EINVAL;
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+
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+ priv->base = res->start;
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+
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+ econfig.size = resource_size(res);
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+ econfig.dev = dev;
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+ econfig.priv = priv;
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+
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+ priv->dev = dev;
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+
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+ nvmem = devm_nvmem_register(dev, &econfig);
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+
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+ return PTR_ERR_OR_ZERO(nvmem);
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+}
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+
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+static const struct of_device_id sec_qfprom_of_match[] = {
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+ { .compatible = "qcom,sec-qfprom" },
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+ {/* sentinel */},
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+};
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+MODULE_DEVICE_TABLE(of, sec_qfprom_of_match);
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+
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+static struct platform_driver qfprom_driver = {
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+ .probe = sec_qfprom_probe,
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+ .driver = {
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+ .name = "qcom_sec_qfprom",
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+ .of_match_table = sec_qfprom_of_match,
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+ },
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+};
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+module_platform_driver(qfprom_driver);
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+MODULE_DESCRIPTION("Qualcomm Secure QFPROM driver");
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+MODULE_LICENSE("GPL");
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