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https://github.com/openwrt/openwrt.git
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b519908e84
Now that 3.13 will be EOL soon, switch to 3.14. Known issues: * 74x164 is not available because upstream dropped non-DT support * jffs2 breaks with SMP Unknown issues: * probably plenty Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 40380
224 lines
6.9 KiB
Diff
224 lines
6.9 KiB
Diff
From c28c639b031385ecf965eecf3bfb532e88044c89 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sun, 15 Dec 2013 20:52:53 +0100
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Subject: [PATCH 30/53] MIPS: BCM63XX: move bcm63xx_init_irq down
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Allows up to drop the prototypes from the top.
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---
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arch/mips/bcm63xx/irq.c | 190 +++++++++++++++++++++++-------------------------
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1 file changed, 92 insertions(+), 98 deletions(-)
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--- a/arch/mips/bcm63xx/irq.c
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+++ b/arch/mips/bcm63xx/irq.c
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@@ -19,13 +19,6 @@
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#include <bcm63xx_io.h>
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#include <bcm63xx_irq.h>
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-static void __dispatch_internal_32(void) __maybe_unused;
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-static void __dispatch_internal_64(void) __maybe_unused;
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-static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
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-static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
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-static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
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-static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
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-
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static u32 irq_stat_addr, irq_mask_addr;
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static void (*dispatch_internal)(void);
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static int is_ext_irq_cascaded;
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@@ -35,97 +28,6 @@ static unsigned int ext_irq_cfg_reg1, ex
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static void (*internal_irq_mask)(unsigned int irq);
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static void (*internal_irq_unmask)(unsigned int irq);
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-static void bcm63xx_init_irq(void)
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-{
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- int irq_bits;
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-
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- irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
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- irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
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-
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- switch (bcm63xx_get_cpu_id()) {
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- case BCM3368_CPU_ID:
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- irq_stat_addr += PERF_IRQSTAT_3368_REG;
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- irq_mask_addr += PERF_IRQMASK_3368_REG;
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- irq_bits = 32;
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- ext_irq_count = 4;
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- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
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- break;
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- case BCM6328_CPU_ID:
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- irq_stat_addr += PERF_IRQSTAT_6328_REG;
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- irq_mask_addr += PERF_IRQMASK_6328_REG;
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- irq_bits = 64;
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- ext_irq_count = 4;
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- is_ext_irq_cascaded = 1;
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- ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
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- ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
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- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
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- break;
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- case BCM6338_CPU_ID:
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- irq_stat_addr += PERF_IRQSTAT_6338_REG;
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- irq_mask_addr += PERF_IRQMASK_6338_REG;
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- irq_bits = 32;
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- ext_irq_count = 4;
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- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
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- break;
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- case BCM6345_CPU_ID:
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- irq_stat_addr += PERF_IRQSTAT_6345_REG;
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- irq_mask_addr += PERF_IRQMASK_6345_REG;
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- irq_bits = 32;
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- ext_irq_count = 4;
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- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
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- break;
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- case BCM6348_CPU_ID:
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- irq_stat_addr += PERF_IRQSTAT_6348_REG;
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- irq_mask_addr += PERF_IRQMASK_6348_REG;
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- irq_bits = 32;
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- ext_irq_count = 4;
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- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
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- break;
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- case BCM6358_CPU_ID:
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- irq_stat_addr += PERF_IRQSTAT_6358_REG;
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- irq_mask_addr += PERF_IRQMASK_6358_REG;
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- irq_bits = 32;
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- ext_irq_count = 4;
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- is_ext_irq_cascaded = 1;
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- ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
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- ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
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- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
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- break;
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- case BCM6362_CPU_ID:
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- irq_stat_addr += PERF_IRQSTAT_6362_REG;
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- irq_mask_addr += PERF_IRQMASK_6362_REG;
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- irq_bits = 64;
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- ext_irq_count = 4;
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- is_ext_irq_cascaded = 1;
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- ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
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- ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
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- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
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- break;
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- case BCM6368_CPU_ID:
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- irq_stat_addr += PERF_IRQSTAT_6368_REG;
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- irq_mask_addr += PERF_IRQMASK_6368_REG;
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- irq_bits = 64;
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- ext_irq_count = 6;
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- is_ext_irq_cascaded = 1;
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- ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
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- ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
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- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
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- ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
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- break;
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- default:
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- BUG();
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- }
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-
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- if (irq_bits == 32) {
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- dispatch_internal = __dispatch_internal_32;
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- internal_irq_mask = __internal_irq_mask_32;
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- internal_irq_unmask = __internal_irq_unmask_32;
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- } else {
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- dispatch_internal = __dispatch_internal_64;
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- internal_irq_mask = __internal_irq_mask_64;
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- internal_irq_unmask = __internal_irq_unmask_64;
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- }
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-}
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static inline u32 get_ext_irq_perf_reg(int irq)
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{
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@@ -451,6 +353,98 @@ static struct irqaction cpu_ext_cascade_
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.flags = IRQF_NO_THREAD,
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};
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+static void bcm63xx_init_irq(void)
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+{
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+ int irq_bits;
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+
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+ irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
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+ irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
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+
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+ switch (bcm63xx_get_cpu_id()) {
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+ case BCM3368_CPU_ID:
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+ irq_stat_addr += PERF_IRQSTAT_3368_REG;
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+ irq_mask_addr += PERF_IRQMASK_3368_REG;
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+ irq_bits = 32;
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+ ext_irq_count = 4;
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+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
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+ break;
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+ case BCM6328_CPU_ID:
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+ irq_stat_addr += PERF_IRQSTAT_6328_REG;
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+ irq_mask_addr += PERF_IRQMASK_6328_REG;
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+ irq_bits = 64;
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+ ext_irq_count = 4;
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+ is_ext_irq_cascaded = 1;
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+ ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
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+ ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
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+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
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+ break;
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+ case BCM6338_CPU_ID:
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+ irq_stat_addr += PERF_IRQSTAT_6338_REG;
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+ irq_mask_addr += PERF_IRQMASK_6338_REG;
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+ irq_bits = 32;
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+ ext_irq_count = 4;
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+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
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+ break;
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+ case BCM6345_CPU_ID:
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+ irq_stat_addr += PERF_IRQSTAT_6345_REG;
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+ irq_mask_addr += PERF_IRQMASK_6345_REG;
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+ irq_bits = 32;
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+ ext_irq_count = 4;
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+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
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+ break;
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+ case BCM6348_CPU_ID:
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+ irq_stat_addr += PERF_IRQSTAT_6348_REG;
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+ irq_mask_addr += PERF_IRQMASK_6348_REG;
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+ irq_bits = 32;
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+ ext_irq_count = 4;
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+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
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+ break;
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+ case BCM6358_CPU_ID:
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+ irq_stat_addr += PERF_IRQSTAT_6358_REG;
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+ irq_mask_addr += PERF_IRQMASK_6358_REG;
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+ irq_bits = 32;
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+ ext_irq_count = 4;
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+ is_ext_irq_cascaded = 1;
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+ ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
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+ ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
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+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
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+ break;
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+ case BCM6362_CPU_ID:
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+ irq_stat_addr += PERF_IRQSTAT_6362_REG;
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+ irq_mask_addr += PERF_IRQMASK_6362_REG;
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+ irq_bits = 64;
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+ ext_irq_count = 4;
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+ is_ext_irq_cascaded = 1;
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+ ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
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+ ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
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+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
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+ break;
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+ case BCM6368_CPU_ID:
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+ irq_stat_addr += PERF_IRQSTAT_6368_REG;
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+ irq_mask_addr += PERF_IRQMASK_6368_REG;
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+ irq_bits = 64;
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+ ext_irq_count = 6;
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+ is_ext_irq_cascaded = 1;
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+ ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
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+ ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
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+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
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+ ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
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+ break;
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+ default:
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+ BUG();
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+ }
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+
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+ if (irq_bits == 32) {
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+ dispatch_internal = __dispatch_internal_32;
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+ internal_irq_mask = __internal_irq_mask_32;
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+ internal_irq_unmask = __internal_irq_unmask_32;
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+ } else {
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+ dispatch_internal = __dispatch_internal_64;
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+ internal_irq_mask = __internal_irq_mask_64;
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+ internal_irq_unmask = __internal_irq_unmask_64;
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+ }
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+}
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+
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void __init arch_init_irq(void)
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{
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int i;
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