mirror of
https://github.com/openwrt/openwrt.git
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8c6f00ef4f
Refresh patches.
Remove upstreamed patches:
- backport/096-mips-math-emu-Write-protect-delay-slot-emulation-pages.patch
- pending/510-f2fs-fix-sanity_check_raw_super-on-big-endian-machines.patch
- brcm2708/950-0415-qmi_wwan-apply-SET_DTR-quirk-to-the-SIMCOM-shared-de.patch
Compile-tested: ar71xx, ath79, brcm2708/bcm27{08,10}, octeon, x86/64
Runtime-tested: ar71xx, ath79, brcm2708/bcm27{08,10}, octeon, x86/64
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
267 lines
9.2 KiB
Diff
267 lines
9.2 KiB
Diff
From 7d83a48b50ac24af7763e7ba5304e9a82f37f014 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.org>
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Date: Fri, 16 Mar 2018 15:04:35 -0700
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Subject: [PATCH 357/454] drm/vc4: Add support for SAND modifier.
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This is the format generated by VC4's H.264 engine, and preferred by
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the ISP as well. By displaying SAND buffers directly, we can avoid
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needing to use the ISP to rewrite the SAND H.264 output to linear
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before display.
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This is a joint effort by Dave Stevenson (who wrote the initial patch
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and DRM demo) and Eric Anholt (drm_fourcc.h generalization, safety
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checks, RGBA support).
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v2: Make the parameter macro give all of the middle 48 bits (suggested
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by Daniels). Fix fourcc_mod_broadcom_mod()'s bits/shift being
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swapped. Mark NV12/21 as supported, not YUV420.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Cc: Daniel Vetter <daniel@ffwll.ch>
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Acked-by: Daniel Stone <daniels@collabora.com> (v1)
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Cc: Boris Brezillon <boris.brezillon@bootlin.com>
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Cc: Maxime Ripard <maxime.ripard@bootlin.com>
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Link: https://patchwork.freedesktop.org/patch/msgid/20180316220435.31416-3-eric@anholt.net
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(cherry picked from commit e065a8dd30af703b4794dc740c0825ee12b92efd)
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---
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drivers/gpu/drm/vc4/vc4_plane.c | 84 ++++++++++++++++++++++++++++++---
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drivers/gpu/drm/vc4/vc4_regs.h | 6 +++
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include/uapi/drm/drm_fourcc.h | 59 +++++++++++++++++++++++
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3 files changed, 142 insertions(+), 7 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_plane.c
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+++ b/drivers/gpu/drm/vc4/vc4_plane.c
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@@ -467,11 +467,13 @@ static int vc4_plane_mode_set(struct drm
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struct drm_framebuffer *fb = state->fb;
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u32 ctl0_offset = vc4_state->dlist_count;
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const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
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+ u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier);
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int num_planes = drm_format_num_planes(format->drm);
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bool covers_screen;
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u32 scl0, scl1, pitch0;
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u32 lbm_size, tiling;
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unsigned long irqflags;
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+ u32 hvs_format = format->hvs;
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int ret, i;
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ret = vc4_plane_setup_clipping_and_scaling(state);
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@@ -511,7 +513,7 @@ static int vc4_plane_mode_set(struct drm
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scl1 = vc4_get_scl_field(state, 0);
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}
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- switch (fb->modifier) {
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+ switch (base_format_mod) {
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case DRM_FORMAT_MOD_LINEAR:
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tiling = SCALER_CTL0_TILING_LINEAR;
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pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
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@@ -534,6 +536,49 @@ static int vc4_plane_mode_set(struct drm
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break;
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}
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+ case DRM_FORMAT_MOD_BROADCOM_SAND64:
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+ case DRM_FORMAT_MOD_BROADCOM_SAND128:
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+ case DRM_FORMAT_MOD_BROADCOM_SAND256: {
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+ uint32_t param = fourcc_mod_broadcom_param(fb->modifier);
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+
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+ /* Column-based NV12 or RGBA.
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+ */
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+ if (fb->format->num_planes > 1) {
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+ if (hvs_format != HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE) {
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+ DRM_DEBUG_KMS("SAND format only valid for NV12/21");
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+ return -EINVAL;
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+ }
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+ hvs_format = HVS_PIXEL_FORMAT_H264;
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+ } else {
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+ if (base_format_mod == DRM_FORMAT_MOD_BROADCOM_SAND256) {
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+ DRM_DEBUG_KMS("SAND256 format only valid for H.264");
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+ return -EINVAL;
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+ }
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+ }
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+
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+ switch (base_format_mod) {
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+ case DRM_FORMAT_MOD_BROADCOM_SAND64:
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+ tiling = SCALER_CTL0_TILING_64B;
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+ break;
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+ case DRM_FORMAT_MOD_BROADCOM_SAND128:
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+ tiling = SCALER_CTL0_TILING_128B;
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+ break;
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+ case DRM_FORMAT_MOD_BROADCOM_SAND256:
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+ tiling = SCALER_CTL0_TILING_256B_OR_T;
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ if (param > SCALER_TILE_HEIGHT_MASK) {
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+ DRM_DEBUG_KMS("SAND height too large (%d)\n", param);
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+ return -EINVAL;
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+ }
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+
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+ pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
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+ break;
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+ }
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+
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default:
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DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
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(long long)fb->modifier);
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@@ -544,7 +589,7 @@ static int vc4_plane_mode_set(struct drm
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vc4_dlist_write(vc4_state,
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SCALER_CTL0_VALID |
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(format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
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- (format->hvs << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
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+ (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
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VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
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(vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
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VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
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@@ -598,8 +643,13 @@ static int vc4_plane_mode_set(struct drm
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/* Pitch word 1/2 */
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for (i = 1; i < num_planes; i++) {
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- vc4_dlist_write(vc4_state,
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- VC4_SET_FIELD(fb->pitches[i], SCALER_SRC_PITCH));
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+ if (hvs_format != HVS_PIXEL_FORMAT_H264) {
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+ vc4_dlist_write(vc4_state,
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+ VC4_SET_FIELD(fb->pitches[i],
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+ SCALER_SRC_PITCH));
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+ } else {
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+ vc4_dlist_write(vc4_state, pitch0);
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+ }
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}
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/* Colorspace conversion words */
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@@ -882,13 +932,30 @@ static bool vc4_format_mod_supported(str
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case DRM_FORMAT_BGR565:
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case DRM_FORMAT_ARGB1555:
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case DRM_FORMAT_XRGB1555:
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- return true;
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+ switch (fourcc_mod_broadcom_mod(modifier)) {
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+ case DRM_FORMAT_MOD_LINEAR:
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+ case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
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+ case DRM_FORMAT_MOD_BROADCOM_SAND64:
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+ case DRM_FORMAT_MOD_BROADCOM_SAND128:
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+ return true;
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+ default:
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+ return false;
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+ }
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+ case DRM_FORMAT_NV12:
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+ case DRM_FORMAT_NV21:
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+ switch (fourcc_mod_broadcom_mod(modifier)) {
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+ case DRM_FORMAT_MOD_LINEAR:
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+ case DRM_FORMAT_MOD_BROADCOM_SAND64:
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+ case DRM_FORMAT_MOD_BROADCOM_SAND128:
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+ case DRM_FORMAT_MOD_BROADCOM_SAND256:
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+ return true;
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+ default:
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+ return false;
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+ }
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case DRM_FORMAT_YUV422:
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case DRM_FORMAT_YVU422:
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case DRM_FORMAT_YUV420:
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case DRM_FORMAT_YVU420:
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- case DRM_FORMAT_NV12:
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- case DRM_FORMAT_NV21:
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case DRM_FORMAT_NV16:
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case DRM_FORMAT_NV61:
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default:
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@@ -918,6 +985,9 @@ struct drm_plane *vc4_plane_init(struct
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unsigned i;
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static const uint64_t modifiers[] = {
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DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
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+ DRM_FORMAT_MOD_BROADCOM_SAND128,
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+ DRM_FORMAT_MOD_BROADCOM_SAND64,
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+ DRM_FORMAT_MOD_BROADCOM_SAND256,
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DRM_FORMAT_MOD_LINEAR,
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DRM_FORMAT_MOD_INVALID
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};
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -1059,6 +1059,12 @@ enum hvs_pixel_format {
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#define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0)
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#define SCALER_SRC_PITCH_SHIFT 0
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+/* PITCH0/1/2 fields for tiled (SAND). */
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+#define SCALER_TILE_SKIP_0_MASK VC4_MASK(18, 16)
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+#define SCALER_TILE_SKIP_0_SHIFT 16
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+#define SCALER_TILE_HEIGHT_MASK VC4_MASK(15, 0)
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+#define SCALER_TILE_HEIGHT_SHIFT 0
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+
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/* PITCH0 fields for T-tiled. */
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#define SCALER_PITCH0_TILE_WIDTH_L_MASK VC4_MASK(22, 16)
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#define SCALER_PITCH0_TILE_WIDTH_L_SHIFT 16
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--- a/include/uapi/drm/drm_fourcc.h
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+++ b/include/uapi/drm/drm_fourcc.h
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@@ -383,6 +383,23 @@ extern "C" {
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#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
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/*
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+ * Some Broadcom modifiers take parameters, for example the number of
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+ * vertical lines in the image. Reserve the lower 32 bits for modifier
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+ * type, and the next 24 bits for parameters. Top 8 bits are the
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+ * vendor code.
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+ */
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+#define __fourcc_mod_broadcom_param_shift 8
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+#define __fourcc_mod_broadcom_param_bits 48
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+#define fourcc_mod_broadcom_code(val, params) \
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+ fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
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+#define fourcc_mod_broadcom_param(m) \
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+ ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
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+ ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
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+#define fourcc_mod_broadcom_mod(m) \
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+ ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
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+ __fourcc_mod_broadcom_param_shift))
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+
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+/*
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* Broadcom VC4 "T" format
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*
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* This is the primary layout that the V3D GPU can texture from (it
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@@ -403,6 +420,48 @@ extern "C" {
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*/
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#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
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+/*
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+ * Broadcom SAND format
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+ *
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+ * This is the native format that the H.264 codec block uses. For VC4
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+ * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
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+ *
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+ * The image can be considered to be split into columns, and the
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+ * columns are placed consecutively into memory. The width of those
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+ * columns can be either 32, 64, 128, or 256 pixels, but in practice
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+ * only 128 pixel columns are used.
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+ *
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+ * The pitch between the start of each column is set to optimally
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+ * switch between SDRAM banks. This is passed as the number of lines
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+ * of column width in the modifier (we can't use the stride value due
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+ * to various core checks that look at it , so you should set the
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+ * stride to width*cpp).
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+ *
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+ * Note that the column height for this format modifier is the same
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+ * for all of the planes, assuming that each column contains both Y
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+ * and UV. Some SAND-using hardware stores UV in a separate tiled
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+ * image from Y to reduce the column height, which is not supported
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+ * with these modifiers.
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+ */
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+
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+#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
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+ fourcc_mod_broadcom_code(2, v)
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+#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
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+ fourcc_mod_broadcom_code(3, v)
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+#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
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+ fourcc_mod_broadcom_code(4, v)
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+#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
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+ fourcc_mod_broadcom_code(5, v)
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+
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+#define DRM_FORMAT_MOD_BROADCOM_SAND32 \
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+ DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
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+#define DRM_FORMAT_MOD_BROADCOM_SAND64 \
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+ DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
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+#define DRM_FORMAT_MOD_BROADCOM_SAND128 \
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+ DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
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+#define DRM_FORMAT_MOD_BROADCOM_SAND256 \
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+ DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
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+
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#if defined(__cplusplus)
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}
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#endif
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