openwrt/target/linux/layerscape/patches-5.4/820-usb-0018-MLK-18794-1-usb-host-xhci-add-.bus_suspend-override.patch
Hauke Mehrtens 32c74552b2 kernel: bump 5.4 to 5.4.168
All updated automatically.

Compile-tested on: lantiq/xrx200, armvirt/64
Runtime-tested on: lantiq/xrx200, armvirt/64

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2021-12-28 19:09:17 +01:00

46 lines
1.7 KiB
Diff

From b5c498026a95f9d80be23711dd6c178cc78d6c33 Mon Sep 17 00:00:00 2001
From: Peter Chen <peter.chen@nxp.com>
Date: Wed, 15 Aug 2018 14:59:55 +0800
Subject: [PATCH] MLK-18794-1 usb: host: xhci: add .bus_suspend override
Some platforms (eg: Cadence USB3) have special requirements to add
platform USB register setting between xhci_bus_suspend and
platform USB controller suspend routine. Eg, The Cadence USB3 needs
RX detect clock switch from 24Mhz to 32Khz within 100ms after set
port to U3, but sometimes, for USB3 HUB connection, the USB2
bus suspend will cost more than 100ms, and introduce the disconnection
before the PHY enters low power mode, then the state is in mess from
controller side.
So in this commit, we introduce .bus_suspend for xhci_driver_overrides
for above use cases.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
(cherry picked from commit f6baa57913ceb40da14a945820cb87e8d6ceb7c7)
---
drivers/usb/host/xhci.c | 2 ++
drivers/usb/host/xhci.h | 1 +
2 files changed, 3 insertions(+)
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -5414,6 +5414,8 @@ void xhci_init_driver(struct hc_driver *
drv->check_bandwidth = over->check_bandwidth;
if (over->reset_bandwidth)
drv->reset_bandwidth = over->reset_bandwidth;
+ if (over->bus_suspend)
+ drv->bus_suspend = over->bus_suspend;
}
}
EXPORT_SYMBOL_GPL(xhci_init_driver);
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1920,6 +1920,7 @@ struct xhci_driver_overrides {
int (*start)(struct usb_hcd *hcd);
int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
+ int (*bus_suspend)(struct usb_hcd *hcd);
};
#define XHCI_CFC_DELAY 10