mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-29 10:08:59 +00:00
b4c02c9998
Removed upstreamed patches:
generic/pending-5.4
445-mtd-spinand-gigadevice-Only-one-dummy-byte-in-QUA.patch
446-mtd-spinand-gigadevice-Add-QE-Bit.patch
pistachio/patches-5.4
150-pwm-img-Fix-null-pointer-access-in-probe.patch
Manually rebased:
layerscape/patches-5.4
801-audio-0011-Revert-ASoC-fsl_sai-add-of_match-data.patch
801-audio-0039-MLK-16224-6-ASoC-fsl_sai-fix-DSD-suspend-resume.patch
801-audio-0073-MLK-21957-3-ASoC-fsl_sai-add-bitcount-and-timestamp-.patch
820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh.patch
All modifications made by update_kernel.sh
Build system: x86_64
Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711,
mvebu (mamba, rango), x86_64, ramips/mt7621
Run-tested: ipq806x/R7800, mvebu (mamba, rango), x86_64, ramips (RT-AC57U)
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
[alter 820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
63 lines
1.9 KiB
Diff
63 lines
1.9 KiB
Diff
From 0d4749abb6f7d042643ba1aa27a7388e8290b6f5 Mon Sep 17 00:00:00 2001
|
|
From: Li Jun <jun.li@nxp.com>
|
|
Date: Tue, 16 Apr 2019 14:02:38 +0800
|
|
Subject: [PATCH] usb: dwc3: use suspend clock from dt to set power down scale
|
|
|
|
Since the new dwc3 use bulk clks including the suspend clk, so we can
|
|
use it to calculate the power down scale value.
|
|
|
|
Acked-by: Peter Chen <peter.chen@nxp.com>
|
|
Signed-off-by: Li Jun <jun.li@nxp.com>
|
|
---
|
|
drivers/usb/dwc3/core.c | 21 +++++++++++++++++++++
|
|
drivers/usb/dwc3/core.h | 1 +
|
|
2 files changed, 22 insertions(+)
|
|
|
|
--- a/drivers/usb/dwc3/core.c
|
|
+++ b/drivers/usb/dwc3/core.c
|
|
@@ -900,6 +900,25 @@ static void dwc3_set_incr_burst_type(str
|
|
dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
|
|
}
|
|
|
|
+static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
|
|
+{
|
|
+ u32 reg, scale;
|
|
+
|
|
+ if (dwc->num_clks == 0)
|
|
+ return;
|
|
+
|
|
+ /*
|
|
+ * The power down scale field specifies how many suspend_clk
|
|
+ * periods fit into a 16KHz clock period. When performing
|
|
+ * the division, round up the remainder.
|
|
+ */
|
|
+ scale = DIV_ROUND_UP(clk_get_rate(dwc->clks[2].clk), 16384);
|
|
+ reg = dwc3_readl(dwc->regs, DWC3_GCTL);
|
|
+ reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
|
|
+ reg |= DWC3_GCTL_PWRDNSCALE(scale);
|
|
+ dwc3_writel(dwc->regs, DWC3_GCTL, reg);
|
|
+}
|
|
+
|
|
/**
|
|
* dwc3_core_init - Low-level initialization of DWC3 Core
|
|
* @dwc: Pointer to our controller context structure
|
|
@@ -924,6 +943,8 @@ static int dwc3_core_init(struct dwc3 *d
|
|
dwc->maximum_speed = USB_SPEED_HIGH;
|
|
}
|
|
|
|
+ dwc3_set_power_down_clk_scale(dwc);
|
|
+
|
|
ret = dwc3_phy_setup(dwc);
|
|
if (ret)
|
|
goto err0;
|
|
--- a/drivers/usb/dwc3/core.h
|
|
+++ b/drivers/usb/dwc3/core.h
|
|
@@ -224,6 +224,7 @@
|
|
|
|
/* Global Configuration Register */
|
|
#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
|
|
+#define DWC3_GCTL_PWRDNSCALE_MASK DWC3_GCTL_PWRDNSCALE(0x1fff)
|
|
#define DWC3_GCTL_U2RSTECN BIT(16)
|
|
#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
|
|
#define DWC3_GCTL_CLK_BUS (0)
|