mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 14:13:16 +00:00
a9dda40fe2
Rebase patches and port SATA driver to work with Linux > 5.13. Tested on Shuttle KD-20. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
45 lines
1.4 KiB
Diff
45 lines
1.4 KiB
Diff
--- a/arch/arm/boot/dts/ox820.dtsi
|
|
+++ b/arch/arm/boot/dts/ox820.dtsi
|
|
@@ -247,6 +247,15 @@
|
|
};
|
|
};
|
|
|
|
+ pcie_phy: pcie-phy@a00000 {
|
|
+ compatible = "oxsemi,ox820-pcie-phy";
|
|
+ reg = <0xa00000 0x10>;
|
|
+ #phy-cells = <0>;
|
|
+ resets = <&reset RESET_PCIEPHY>;
|
|
+ reset-names = "phy";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
sys: sys-ctrl@e00000 {
|
|
compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
|
|
reg = <0xe00000 0x200000>;
|
|
--- a/drivers/phy/Kconfig
|
|
+++ b/drivers/phy/Kconfig
|
|
@@ -35,6 +35,13 @@ config PHY_LPC18XX_USB_OTG
|
|
This driver is need for USB0 support on LPC18xx/43xx and takes
|
|
care of enabling and clock setup.
|
|
|
|
+config PHY_OXNAS
|
|
+ tristate "Oxford Semi. OX820 PCI-E PHY support"
|
|
+ depends on HAS_IOMEM && OF && (ARM || COMPILE_TEST)
|
|
+ select GENERIC_PHY
|
|
+ help
|
|
+ This option enables support for OXNAS OX820 SoC PCIE PHY.
|
|
+
|
|
config PHY_PISTACHIO_USB
|
|
tristate "IMG Pistachio USB2.0 PHY driver"
|
|
depends on MIPS || COMPILE_TEST
|
|
--- a/drivers/phy/Makefile
|
|
+++ b/drivers/phy/Makefile
|
|
@@ -7,6 +7,7 @@ obj-$(CONFIG_GENERIC_PHY) += phy-core.o
|
|
obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o
|
|
obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o
|
|
obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
|
|
+obj-$(CONFIG_PHY_OXNAS) += phy-oxnas-pcie.o
|
|
obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
|
|
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
|
|
obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
|