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56b19f0d50
8989bad54113 net: phy: realtek: add RTL8125D-internal PHY
f87a17ed3b51 net: phy: realtek: merge the drivers for internal NBase-T PHY's
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
(cherry picked from commit fedb1f86b5)
137 lines
4.7 KiB
Diff
137 lines
4.7 KiB
Diff
From f87a17ed3b51fba4dfdd8f8b643b5423a85fc551 Mon Sep 17 00:00:00 2001
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From: Heiner Kallweit <hkallweit1@gmail.com>
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Date: Tue, 15 Oct 2024 07:47:14 +0200
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Subject: [PATCH] net: phy: realtek: merge the drivers for internal NBase-T
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PHY's
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The Realtek RTL8125/RTL8126 NBase-T MAC/PHY chips have internal PHY's
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which are register-compatible, at least for the registers we use here.
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So let's use just one PHY driver to support all of them.
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These internal PHY's exist also as external C45 PHY's, but on the
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internal PHY's no access to MMD registers is possible. This can be
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used to differentiate between the internal and external version.
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As a side effect the drivers for two now external-only drivers don't
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require read_mmd/write_mmd hooks any longer.
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Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
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Link: https://patch.msgid.link/c57081a6-811f-4571-ab35-34f4ca6de9af@gmail.com
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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drivers/net/phy/realtek.c | 53 +++++++++++++++++++++++++++++++--------
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1 file changed, 43 insertions(+), 10 deletions(-)
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--- a/drivers/net/phy/realtek.c
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+++ b/drivers/net/phy/realtek.c
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@@ -95,6 +95,7 @@
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#define RTL_GENERIC_PHYID 0x001cc800
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#define RTL_8211FVD_PHYID 0x001cc878
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+#define RTL_8221B 0x001cc840
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#define RTL_8221B_VB_CG 0x001cc849
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#define RTL_8221B_VN_CG 0x001cc84a
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#define RTL_8251B 0x001cc862
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@@ -1077,6 +1078,23 @@ static bool rtlgen_supports_2_5gbps(stru
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return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
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}
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+/* On internal PHY's MMD reads over C22 always return 0.
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+ * Check a MMD register which is known to be non-zero.
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+ */
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+static bool rtlgen_supports_mmd(struct phy_device *phydev)
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+{
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+ int val;
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+
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+ phy_lock_mdio_bus(phydev);
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+ __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS);
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+ __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE);
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+ __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR);
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+ val = __phy_read(phydev, MII_MMD_DATA);
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+ phy_unlock_mdio_bus(phydev);
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+
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+ return val > 0;
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+}
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+
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static int rtlgen_match_phy_device(struct phy_device *phydev)
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{
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return phydev->phy_id == RTL_GENERIC_PHYID &&
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@@ -1086,7 +1104,8 @@ static int rtlgen_match_phy_device(struc
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static int rtl8226_match_phy_device(struct phy_device *phydev)
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{
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return phydev->phy_id == RTL_GENERIC_PHYID &&
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- rtlgen_supports_2_5gbps(phydev);
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+ rtlgen_supports_2_5gbps(phydev) &&
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+ rtlgen_supports_mmd(phydev);
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}
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static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
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@@ -1098,6 +1117,11 @@ static int rtlgen_is_c45_match(struct ph
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return !is_c45 && (id == phydev->phy_id);
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}
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+static int rtl8221b_match_phy_device(struct phy_device *phydev)
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+{
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+ return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev);
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+}
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+
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static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev)
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{
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return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);
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@@ -1118,9 +1142,21 @@ static int rtl8221b_vn_cg_c45_match_phy_
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return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true);
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}
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-static int rtl8251b_c22_match_phy_device(struct phy_device *phydev)
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+static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev)
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{
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- return rtlgen_is_c45_match(phydev, RTL_8251B, false);
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+ if (phydev->is_c45)
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+ return false;
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+
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+ switch (phydev->phy_id) {
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+ case RTL_GENERIC_PHYID:
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+ case RTL_8221B:
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+ case RTL_8251B:
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+ break;
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+ default:
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+ return false;
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+ }
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+
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+ return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev);
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}
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static int rtl8251b_c45_match_phy_device(struct phy_device *phydev)
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@@ -1382,10 +1418,8 @@ static struct phy_driver realtek_drvs[]
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.resume = rtlgen_resume,
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.read_page = rtl821x_read_page,
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.write_page = rtl821x_write_page,
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- .read_mmd = rtl822x_read_mmd,
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- .write_mmd = rtl822x_write_mmd,
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}, {
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- PHY_ID_MATCH_EXACT(0x001cc840),
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+ .match_phy_device = rtl8221b_match_phy_device,
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.name = "RTL8226B_RTL8221B 2.5Gbps PHY",
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.get_features = rtl822x_get_features,
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.config_aneg = rtl822x_config_aneg,
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@@ -1396,8 +1430,6 @@ static struct phy_driver realtek_drvs[]
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.resume = rtlgen_resume,
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.read_page = rtl821x_read_page,
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.write_page = rtl821x_write_page,
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- .read_mmd = rtl822x_read_mmd,
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- .write_mmd = rtl822x_write_mmd,
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}, {
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PHY_ID_MATCH_EXACT(0x001cc838),
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.name = "RTL8226-CG 2.5Gbps PHY",
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@@ -1475,8 +1507,9 @@ static struct phy_driver realtek_drvs[]
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.read_page = rtl821x_read_page,
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.write_page = rtl821x_write_page,
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}, {
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- .match_phy_device = rtl8251b_c22_match_phy_device,
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- .name = "RTL8126A-internal 5Gbps PHY",
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+ .match_phy_device = rtl_internal_nbaset_match_phy_device,
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+ .name = "Realtek Internal NBASE-T PHY",
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+ .flags = PHY_IS_INTERNAL,
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.get_features = rtl822x_get_features,
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.config_aneg = rtl822x_config_aneg,
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.read_status = rtl822x_read_status,
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