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53f338be43
Add pending patch for ipq4019 MDIO MDC rate fix. The divisor was never actually set resulting in the MDC rate running at a very low speed. The same MDIO is used on ipq807x where Aquantia PHY are commonly used where MDIO is used to load the PHY firmware. Running at higher speed is required to make the firmware load faster as it does reduce load time from 60+ second to 5-6 seconds. Add as pending as upstream there seems to be some conflicts with quic and me and it might take lots of time before this is effectively merged upstream. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
43 lines
1.6 KiB
Diff
43 lines
1.6 KiB
Diff
From 85e2038891989e41bc62f6a4625fd5865da8a1a2 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Wed, 24 Jan 2024 19:17:02 +0100
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Subject: [PATCH 1/3] dt-bindings: net: ipq4019-mdio: document now supported
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clock-frequency
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Document support for clock-frequency and add details on why this
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property is needed and what values are supported.
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From internal documentation, while other values are supported, the
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correct function of the MDIO bus is not assured hence add only the
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suggested supported values to the property enum.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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.../bindings/net/qcom,ipq4019-mdio.yaml | 15 +++++++++++++++
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1 file changed, 15 insertions(+)
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--- a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml
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+++ b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml
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@@ -38,6 +38,21 @@ properties:
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MDIO clock source frequency fixed to 100MHZ, this clock should be specified
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by the platform IPQ807x, IPQ60xx and IPQ50xx.
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+ clock-frequency:
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+ description:
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+ The MDIO bus clock that must be output by the MDIO bus hardware, if
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+ absent, the default hardware values are used.
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+
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+ MDC rate is feed by an external clock (fixed 100MHz) and is divider
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+ internally. The default divider is /256 resulting in the default rate
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+ applied of 390KHz.
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+
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+ To follow 802.3 standard that instruct up to 2.5MHz by default, if
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+ this property is not declared and the divider is set to /256, by
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+ default 1.5625Mhz is select.
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+ enum: [ 390625, 781250, 1562500, 3125000, 6250000, 12500000 ]
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+ default: 1562500
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+
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required:
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- compatible
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- reg
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