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e58cd453d5
Add kernel support for SAMA7G5 by back-porting mainline kernel patches. Among SAMA7G5 features could be remembered: - ARM Cortex-A7 - double data rate multi-port dynamic RAM controller supporting DDR2, DDR3, DDR3L, LPDDR2, LPDDR3 up to 533MHz - peripherals for audio, video processing - 1 gigabit + 1 megabit Ethernet controllers - 6 CAN controllers - trust zone support - DVFS for CPU - criptography IPs Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
61 lines
2.3 KiB
Diff
61 lines
2.3 KiB
Diff
From bf032d1a0105939b90072914d88181fbe6187f43 Mon Sep 17 00:00:00 2001
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From: Eugen Hristev <eugen.hristev@microchip.com>
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Date: Tue, 13 Apr 2021 12:57:24 +0200
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Subject: [PATCH 182/247] media: atmel: atmel-isc-regs: add additional fields
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for sama7g5 type pipeline
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Add additional fields for registers present in sama7g5 type pipeline.
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Extend register masks for additional bits in sama7g5 type pipeline registers.
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Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
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Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
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Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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---
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drivers/media/platform/atmel/atmel-isc-regs.h | 16 ++++++++++++++--
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1 file changed, 14 insertions(+), 2 deletions(-)
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diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h
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index 457eed74cda9..5f99bf7717c1 100644
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--- a/drivers/media/platform/atmel/atmel-isc-regs.h
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+++ b/drivers/media/platform/atmel/atmel-isc-regs.h
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@@ -289,8 +289,18 @@
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#define ISC_RLP_CFG_MODE_ARGB32 0xa
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#define ISC_RLP_CFG_MODE_YYCC 0xb
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#define ISC_RLP_CFG_MODE_YYCC_LIMITED 0xc
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+#define ISC_RLP_CFG_MODE_YCYC 0xd
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#define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0)
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+#define ISC_RLP_CFG_LSH BIT(5)
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+
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+#define ISC_RLP_CFG_YMODE_YUYV (3 << 6)
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+#define ISC_RLP_CFG_YMODE_YVYU (2 << 6)
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+#define ISC_RLP_CFG_YMODE_VYUY (0 << 6)
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+#define ISC_RLP_CFG_YMODE_UYVY (1 << 6)
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+
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+#define ISC_RLP_CFG_YMODE_MASK GENMASK(7, 6)
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+
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/* Offset for HIS register specific to sama5d2 product */
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#define ISC_SAMA5D2_HIS_OFFSET 0
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/* Histogram Control Register */
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@@ -332,13 +342,15 @@
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#define ISC_DCFG_YMBSIZE_BEATS4 (0x1 << 4)
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#define ISC_DCFG_YMBSIZE_BEATS8 (0x2 << 4)
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#define ISC_DCFG_YMBSIZE_BEATS16 (0x3 << 4)
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-#define ISC_DCFG_YMBSIZE_MASK GENMASK(5, 4)
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+#define ISC_DCFG_YMBSIZE_BEATS32 (0x4 << 4)
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+#define ISC_DCFG_YMBSIZE_MASK GENMASK(6, 4)
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#define ISC_DCFG_CMBSIZE_SINGLE (0x0 << 8)
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#define ISC_DCFG_CMBSIZE_BEATS4 (0x1 << 8)
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#define ISC_DCFG_CMBSIZE_BEATS8 (0x2 << 8)
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#define ISC_DCFG_CMBSIZE_BEATS16 (0x3 << 8)
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-#define ISC_DCFG_CMBSIZE_MASK GENMASK(9, 8)
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+#define ISC_DCFG_CMBSIZE_BEATS32 (0x4 << 8)
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+#define ISC_DCFG_CMBSIZE_MASK GENMASK(10, 8)
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/* DMA Control Register */
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#define ISC_DCTRL 0x000003e4
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--
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2.32.0
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