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e58cd453d5
Add kernel support for SAMA7G5 by back-porting mainline kernel patches. Among SAMA7G5 features could be remembered: - ARM Cortex-A7 - double data rate multi-port dynamic RAM controller supporting DDR2, DDR3, DDR3L, LPDDR2, LPDDR3 up to 533MHz - peripherals for audio, video processing - 1 gigabit + 1 megabit Ethernet controllers - 6 CAN controllers - trust zone support - DVFS for CPU - criptography IPs Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
127 lines
4.5 KiB
Diff
127 lines
4.5 KiB
Diff
From bd819c78346012ae0627b1cd4f6ceb1b51162c71 Mon Sep 17 00:00:00 2001
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From: Claudiu Beznea <claudiu.beznea@microchip.com>
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Date: Wed, 27 Jan 2021 13:45:44 +0200
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Subject: [PATCH 146/247] pinctrl: at91-pio4: add support for slew-rate
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SAMA7G5 supports slew rate configuration. Adapt the driver for this.
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For output switching frequencies lower than 50MHz the slew rate needs to
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be enabled. Since most of the pins on SAMA7G5 fall into this category
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enabled the slew rate by default.
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
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Link: https://lore.kernel.org/r/1611747945-29960-3-git-send-email-claudiu.beznea@microchip.com
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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drivers/pinctrl/pinctrl-at91-pio4.c | 27 +++++++++++++++++++++++++++
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1 file changed, 27 insertions(+)
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diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c
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index d267367d94b9..f202cdb6dc3c 100644
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--- a/drivers/pinctrl/pinctrl-at91-pio4.c
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+++ b/drivers/pinctrl/pinctrl-at91-pio4.c
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@@ -36,6 +36,7 @@
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#define ATMEL_PIO_DIR_MASK BIT(8)
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#define ATMEL_PIO_PUEN_MASK BIT(9)
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#define ATMEL_PIO_PDEN_MASK BIT(10)
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+#define ATMEL_PIO_SR_MASK BIT(11)
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#define ATMEL_PIO_IFEN_MASK BIT(12)
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#define ATMEL_PIO_IFSCEN_MASK BIT(13)
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#define ATMEL_PIO_OPD_MASK BIT(14)
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@@ -76,10 +77,12 @@
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* @nbanks: number of PIO banks
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* @last_bank_count: number of lines in the last bank (can be less than
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* the rest of the banks).
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+ * @slew_rate_support: slew rate support
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*/
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struct atmel_pioctrl_data {
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unsigned nbanks;
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unsigned last_bank_count;
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+ unsigned int slew_rate_support;
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};
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struct atmel_group {
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@@ -117,6 +120,7 @@ struct atmel_pin {
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* @pm_suspend_backup: backup/restore register values on suspend/resume
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* @dev: device entry for the Atmel PIO controller.
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* @node: node of the Atmel PIO controller.
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+ * @slew_rate_support: slew rate support
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*/
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struct atmel_pioctrl {
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void __iomem *reg_base;
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@@ -138,6 +142,7 @@ struct atmel_pioctrl {
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} *pm_suspend_backup;
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struct device *dev;
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struct device_node *node;
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+ unsigned int slew_rate_support;
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};
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static const char * const atmel_functions[] = {
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@@ -760,6 +765,13 @@ static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
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return -EINVAL;
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arg = 1;
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break;
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+ case PIN_CONFIG_SLEW_RATE:
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+ if (!atmel_pioctrl->slew_rate_support)
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+ return -EOPNOTSUPP;
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+ if (!(res & ATMEL_PIO_SR_MASK))
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+ return -EINVAL;
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+ arg = 1;
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+ break;
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case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
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if (!(res & ATMEL_PIO_DRVSTR_MASK))
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return -EINVAL;
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@@ -793,6 +805,10 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
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dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
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__func__, pin_id, configs[i]);
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+ /* Keep slew rate enabled by default. */
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+ if (atmel_pioctrl->slew_rate_support)
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+ conf |= ATMEL_PIO_SR_MASK;
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+
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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conf &= (~ATMEL_PIO_PUEN_MASK);
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@@ -850,6 +866,13 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
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ATMEL_PIO_SODR);
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}
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break;
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+ case PIN_CONFIG_SLEW_RATE:
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+ if (!atmel_pioctrl->slew_rate_support)
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+ break;
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+ /* And remove it if explicitly requested. */
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+ if (arg == 0)
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+ conf &= ~ATMEL_PIO_SR_MASK;
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+ break;
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case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
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switch (arg) {
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case ATMEL_PIO_DRVSTR_LO:
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@@ -901,6 +924,8 @@ static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
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seq_printf(s, "%s ", "open-drain");
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if (conf & ATMEL_PIO_SCHMITT_MASK)
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seq_printf(s, "%s ", "schmitt");
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+ if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK))
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+ seq_printf(s, "%s ", "slew-rate");
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if (conf & ATMEL_PIO_DRVSTR_MASK) {
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switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
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case ATMEL_PIO_DRVSTR_ME:
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@@ -994,6 +1019,7 @@ static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
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static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
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.nbanks = 5,
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.last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */
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+ .slew_rate_support = 1,
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};
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static const struct of_device_id atmel_pctrl_of_match[] = {
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@@ -1039,6 +1065,7 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
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atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;
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atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;
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}
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+ atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support;
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atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(atmel_pioctrl->reg_base))
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--
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2.32.0
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