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11d88dee1c
Reorder and update existing patches
Signed-off-by: Felix Fietkau <nbd@nbd.name>
(cherry picked from commit 6407ef8d2b)
[rmilecki: rebase & fix mt76 compilation]
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
47 lines
1.8 KiB
Diff
47 lines
1.8 KiB
Diff
From dee3f591103910c8d8b2a6d57879ccd2a4be4b10 Mon Sep 17 00:00:00 2001
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Message-ID: <dee3f591103910c8d8b2a6d57879ccd2a4be4b10.1706067287.git.daniel@makrotopia.org>
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Wed, 24 Jan 2024 03:19:49 +0000
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Subject: [PATCH net] net: ethernet: mtk_eth_soc: set coherent mask to get PPE
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working
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To: Felix Fietkau <nbd@nbd.name>,
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Sean Wang <sean.wang@mediatek.com>,
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Mark Lee <Mark-MC.Lee@mediatek.com>,
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Lorenzo Bianconi <lorenzo@kernel.org>,
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David S. Miller <davem@davemloft.net>,
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Eric Dumazet <edumazet@google.com>,
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Jakub Kicinski <kuba@kernel.org>,
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Paolo Abeni <pabeni@redhat.com>,
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Matthias Brugger <matthias.bgg@gmail.com>,
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AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
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Daniel Golle <daniel@makrotopia.org>,
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netdev@vger.kernel.org,
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linux-kernel@vger.kernel.org,
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linux-arm-kernel@lists.infradead.org,
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linux-mediatek@lists.infradead.org
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Set DMA coherent mask to 32-bit which makes PPE offloading engine start
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working on BPi-R4 which got 4 GiB of RAM.
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Fixes: 2d75891ebc09 ("net: ethernet: mtk_eth_soc: support 36-bit DMA addressing on MT7988")
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Suggested-by: Elad Yifee <eladwf@users.github.com>
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 5 ++++-
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1 file changed, 4 insertions(+), 1 deletion(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -4831,7 +4831,10 @@ static int mtk_probe(struct platform_dev
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}
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
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- err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36));
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+ err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36));
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+ if (!err)
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+ err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
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+
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if (err) {
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dev_err(&pdev->dev, "Wrong DMA config\n");
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return -EINVAL;
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