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43d1d88510
Tegra 2 processors have only 16 double-precision registers. The change introduced by8dcc108760("toolchain: ARM: Fix toolchain compilation for gcc 8.x") switched accidentally the toolchain for tegra target to cpu type with 32 double-precision registers. This stems from gcc defaults which assume "vfpv3-d32" if only "vfpv3" as mfpu is specified. That change resulted in unusable image, in which kernel will kill userspace as soon as it causing "Illegal instruction". Ref: https://forum.openwrt.org/t/gcc-was-broken-on-mvebu-armada-370-device-after-commit-on-2019-03-25/43272 Fixes:8dcc108760("toolchain: ARM: Fix toolchain compilation for gcc 8.x") Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
30 lines
676 B
Makefile
30 lines
676 B
Makefile
#
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# Copyright (C) 2017-2019 Tomasz Maciej Nowak <tomek_n@o2.pl>
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#
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# This is free software, licensed under the GNU General Public License v2.
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# See /LICENSE for more information.
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#
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include $(TOPDIR)/rules.mk
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ARCH := arm
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BOARD := tegra
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BOARDNAME := NVIDIA Tegra
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FEATURES := audio boot-part display ext4 fpu gpio pci pcie rootfs-part rtc squashfs usb
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CPU_TYPE := cortex-a9
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CPU_SUBTYPE := vfpv3-d16
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KERNEL_PATCHVER := 5.4
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KERNEL_TESTING_PATCHVER := 5.4
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include $(INCLUDE_DIR)/target.mk
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KERNELNAME := zImage dtbs
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DEFAULT_PACKAGES += e2fsprogs mkf2fs partx-utils
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define Target/Description
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Build firmware image for NVIDIA Tegra SoC devices.
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endef
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$(eval $(call BuildTarget))
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