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7d7aa2fd92
This change makes the names of Broadcom targets consistent by using the common notation based on SoC/CPU ID (which is used internally anyway), bcmXXXX instead of brcmXXXX. This is even used for target TITLE in make menuconfig already, only the short target name used brcm so far. Despite, since subtargets range from bcm2708 to bcm2711, it seems appropriate to use bcm27xx instead of bcm2708 (again, as already done for BOARDNAME). This also renames the packages brcm2708-userland and brcm2708-gpu-fw. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de> Acked-by: Álvaro Fernández Rojas <noltari@gmail.com>
1130 lines
26 KiB
Diff
1130 lines
26 KiB
Diff
From ff78cbcd8d7d656a5f43abd2c744e610b8c6c740 Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.org>
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Date: Wed, 29 May 2019 13:54:21 +0100
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Subject: [PATCH] ARM: dts: Add bcm2711-rpi-4-b.dts and components
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Signed-off-by: Phil Elwell <phil@raspberrypi.org>
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---
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arch/arm/boot/dts/Makefile | 1 +
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arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 320 ++++++++++++
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arch/arm/boot/dts/bcm2711.dtsi | 50 ++
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arch/arm/boot/dts/bcm2838.dtsi | 724 ++++++++++++++++++++++++++
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4 files changed, 1095 insertions(+)
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create mode 100644 arch/arm/boot/dts/bcm2711-rpi-4-b.dts
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create mode 100644 arch/arm/boot/dts/bcm2711.dtsi
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create mode 100644 arch/arm/boot/dts/bcm2838.dtsi
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
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bcm2708-rpi-zero-w.dtb \
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bcm2709-rpi-2-b.dtb \
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bcm2710-rpi-3-b.dtb \
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+ bcm2711-rpi-4-b.dtb \
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bcm2710-rpi-3-b-plus.dtb \
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bcm2710-rpi-cm3.dtb
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--- /dev/null
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+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
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@@ -0,0 +1,320 @@
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+/dts-v1/;
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+
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+#include "bcm2711.dtsi"
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+
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+/ {
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+ compatible = "raspberrypi,4-model-b", "brcm,bcm2838", "brcm,bcm2837";
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+ model = "Raspberry Pi 4 Model B";
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+
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+ memory {
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+ device_type = "memory";
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+ reg = <0x0 0x0 0x0>;
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+ };
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+
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+ chosen {
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+ bootargs = "8250.nr_uarts=1 cma=64M";
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+ };
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+
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+ aliases {
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+ serial0 = &uart1;
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+ serial1 = &uart0;
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+ mmc0 = &emmc2;
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+ mmc1 = &mmcnr;
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+ mmc2 = &sdhost;
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+ /delete-property/ ethernet;
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+ /delete-property/ intc;
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+ ethernet0 = &genet;
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+ };
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+};
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+
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+&soc {
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+ virtgpio: virtgpio {
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+ compatible = "brcm,bcm2835-virtgpio";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ firmware = <&firmware>;
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+ status = "okay";
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+ };
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+};
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+
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+&mmcnr {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&sdio_pins>;
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+ bus-width = <4>;
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+ status = "okay";
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+};
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+
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+&firmware {
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+ expgpio: expgpio {
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+ compatible = "raspberrypi,firmware-gpio";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ status = "okay";
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+ };
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+};
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+
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+&uart0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart0_pins &bt_pins>;
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+ status = "okay";
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+};
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+
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+&uart1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart1_pins>;
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+ status = "okay";
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+};
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+
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+&spi0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi0_pins &spi0_cs_pins>;
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+ cs-gpios = <&gpio 8 1>, <&gpio 7 1>;
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+
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+ spidev0: spidev@0{
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+ compatible = "spidev";
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+ reg = <0>; /* CE0 */
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ spi-max-frequency = <125000000>;
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+ };
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+
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+ spidev1: spidev@1{
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+ compatible = "spidev";
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+ reg = <1>; /* CE1 */
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ spi-max-frequency = <125000000>;
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+ };
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+};
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+
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+// =============================================
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+// Board specific stuff here
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+
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+/ {
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+
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+ sd_io_1v8_reg: sd_io_1v8_reg {
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+ status = "okay";
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+ compatible = "regulator-gpio";
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+ vin-supply = <&vdd_5v0_reg>;
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+ regulator-name = "vdd-sd-io";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ regulator-settling-time-us = <5000>;
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+
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+ gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;
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+ states = <1800000 0x1
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+ 3300000 0x0>;
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+ };
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+};
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+
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+&sdhost {
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+ status = "disabled";
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+};
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+
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+&emmc2 {
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+ status = "okay";
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+ broken-cd;
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+ vqmmc-supply = <&sd_io_1v8_reg>;
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+};
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+
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+&leds {
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+ act_led: act {
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+ label = "led0";
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+ linux,default-trigger = "mmc0";
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+ gpios = <&gpio 42 0>;
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+ };
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+
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+ pwr_led: pwr {
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+ label = "led1";
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+ linux,default-trigger = "input";
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+ gpios = <&expgpio 2 0>;
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+ };
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+};
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+
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+&audio {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&audio_pins>;
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+};
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+
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+&sdhost_gpio48 {
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+ brcm,pins = <22 23 24 25 26 27>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+};
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+
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+&gpio {
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+ spi0_pins: spi0_pins {
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+ brcm,pins = <9 10 11>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+
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+ spi0_cs_pins: spi0_cs_pins {
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+ brcm,pins = <8 7>;
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+ brcm,function = <BCM2835_FSEL_GPIO_OUT>;
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+ };
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+
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+ spi3_pins: spi3_pins {
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+ brcm,pins = <1 2 3>;
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+ brcm,function = <BCM2835_FSEL_ALT3>;
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+ };
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+
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+ spi3_cs_pins: spi3_cs_pins {
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+ brcm,pins = <0 24>;
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+ brcm,function = <BCM2835_FSEL_GPIO_OUT>;
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+ };
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+
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+ spi4_pins: spi4_pins {
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+ brcm,pins = <5 6 7>;
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+ brcm,function = <BCM2835_FSEL_ALT3>;
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+ };
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+
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+ spi4_cs_pins: spi4_cs_pins {
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+ brcm,pins = <4 25>;
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+ brcm,function = <BCM2835_FSEL_GPIO_OUT>;
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+ };
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+
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+ spi5_pins: spi5_pins {
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+ brcm,pins = <13 14 15>;
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+ brcm,function = <BCM2835_FSEL_ALT3>;
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+ };
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+
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+ spi5_cs_pins: spi5_cs_pins {
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+ brcm,pins = <12 26>;
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+ brcm,function = <BCM2835_FSEL_GPIO_OUT>;
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+ };
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+
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+ spi6_pins: spi6_pins {
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+ brcm,pins = <19 20 21>;
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+ brcm,function = <BCM2835_FSEL_ALT3>;
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+ };
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+
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+ spi6_cs_pins: spi6_cs_pins {
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+ brcm,pins = <18 27>;
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+ brcm,function = <BCM2835_FSEL_GPIO_OUT>;
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+ };
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+
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+ i2c0_pins: i2c0 {
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+ brcm,pins = <0 1>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+
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+ i2c1_pins: i2c1 {
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+ brcm,pins = <2 3>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+
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+ i2c3_pins: i2c3 {
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+ brcm,pins = <4 5>;
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+ brcm,function = <BCM2835_FSEL_ALT5>;
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+ };
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+
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+ i2c4_pins: i2c4 {
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+ brcm,pins = <8 9>;
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+ brcm,function = <BCM2835_FSEL_ALT5>;
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+ };
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+
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+ i2c5_pins: i2c5 {
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+ brcm,pins = <12 13>;
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+ brcm,function = <BCM2835_FSEL_ALT5>;
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+ };
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+
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+ i2c6_pins: i2c6 {
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+ brcm,pins = <22 23>;
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+ brcm,function = <BCM2835_FSEL_ALT5>;
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+ };
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+
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+ i2s_pins: i2s {
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+ brcm,pins = <18 19 20 21>;
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+ brcm,function = <BCM2835_FSEL_ALT0>;
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+ };
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+
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+ sdio_pins: sdio_pins {
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+ brcm,pins = <34 35 36 37 38 39>;
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+ brcm,function = <BCM2835_FSEL_ALT3>; // alt3 = SD1
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+ brcm,pull = <0 2 2 2 2 2>;
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+ };
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+
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+ bt_pins: bt_pins {
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+ brcm,pins = "-"; // non-empty to keep btuart happy, //4 = 0
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+ // to fool pinctrl
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+ brcm,function = <0>;
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+ brcm,pull = <2>;
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+ };
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+
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+ uart0_pins: uart0_pins {
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+ brcm,pins = <32 33>;
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+ brcm,function = <BCM2835_FSEL_ALT3>;
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+ brcm,pull = <0 2>;
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+ };
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+
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+ uart1_pins: uart1_pins {
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+ brcm,pins;
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+ brcm,function;
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+ brcm,pull;
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+ };
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+
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+ uart2_pins: uart2_pins {
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+ brcm,pins = <0 1>;
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+ brcm,function = <BCM2835_FSEL_ALT4>;
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+ brcm,pull = <0 2>;
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+ };
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+
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+ uart3_pins: uart3_pins {
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+ brcm,pins = <4 5>;
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+ brcm,function = <BCM2835_FSEL_ALT4>;
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+ brcm,pull = <0 2>;
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+ };
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+
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+ uart4_pins: uart4_pins {
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+ brcm,pins = <8 9>;
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+ brcm,function = <BCM2835_FSEL_ALT4>;
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+ brcm,pull = <0 2>;
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+ };
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+
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+ uart5_pins: uart5_pins {
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+ brcm,pins = <12 13>;
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+ brcm,function = <BCM2835_FSEL_ALT4>;
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+ brcm,pull = <0 2>;
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+ };
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+
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+ audio_pins: audio_pins {
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+ brcm,pins = <40 41>;
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+ brcm,function = <4>;
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+ };
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+};
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+
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+&i2c0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c0_pins>;
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+ clock-frequency = <100000>;
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+};
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+
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+&i2c1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c1_pins>;
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+ clock-frequency = <100000>;
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+};
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+
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+&i2c2 {
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+ clock-frequency = <100000>;
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+};
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+
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+&i2s {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2s_pins>;
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+};
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+
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+/ {
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+ __overrides__ {
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+ act_led_gpio = <&act_led>,"gpios:4";
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+ act_led_activelow = <&act_led>,"gpios:8";
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+ act_led_trigger = <&act_led>,"linux,default-trigger";
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+
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+ pwr_led_gpio = <&pwr_led>,"gpios:4";
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+ pwr_led_activelow = <&pwr_led>,"gpios:8";
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+ pwr_led_trigger = <&pwr_led>,"linux,default-trigger";
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm/boot/dts/bcm2711.dtsi
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@@ -0,0 +1,50 @@
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+#include "bcm2838.dtsi"
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+#include "bcm270x.dtsi"
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+#include "bcm2708-rpi.dtsi"
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+
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+/ {
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+ soc {
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+ /delete-node/ mailbox@7e00b840;
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+ /delete-node/ v3d@7ec00000;
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+ };
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+
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+ __overrides__ {
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+ arm_freq;
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+ };
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+};
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+
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+&dma {
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+ brcm,dma-channel-mask = <0x7ef5>;
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+};
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+
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+&txp {
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+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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+};
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+
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+&firmwarekms {
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+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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+};
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+
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+&smi {
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+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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+};
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+
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+&mmc {
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+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
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+};
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+
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+&mmcnr {
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+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
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+};
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+
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+&usb {
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+ reg = <0x7e980000 0x10000>,
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+ <0x7e00b200 0x200>;
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+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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+};
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+
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+&gpio {
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+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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+};
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--- /dev/null
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+++ b/arch/arm/boot/dts/bcm2838.dtsi
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@@ -0,0 +1,724 @@
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+// SPDX-License-Identifier: GPL-2.0
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+#include "bcm283x.dtsi"
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+
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/soc/bcm2835-pm.h>
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+
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+/ {
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+ compatible = "brcm,bcm2838", "brcm,bcm2837";
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+
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+ interrupt-parent = <&gicv2>;
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+
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+ soc {
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+ ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
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+ <0x7c000000 0x0 0xfc000000 0x02000000>,
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+ <0x40000000 0x0 0xff800000 0x00800000>;
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+ /* Emulate a contiguous 30-bit address range for DMA */
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+ dma-ranges = <0xc0000000 0x0 0x00000000 0x3c000000>;
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+
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+ /delete-node/ mailbox@7e00b840;
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+ /delete-node/ interrupt-controller@7e00f300;
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+
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+ local_intc: local_intc@40000000 {
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+ compatible = "brcm,bcm2836-l1-intc";
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+ reg = <0x40000000 0x100>;
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+ };
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+
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+ gicv2: gic400@40041000 {
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ compatible = "arm,gic-400";
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+ reg = <0x40041000 0x1000>,
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+ <0x40042000 0x2000>,
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+ <0x40046000 0x2000>,
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+ <0x40048000 0x2000>;
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+ };
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+
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+ thermal: thermal@7d5d2200 {
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+ compatible = "brcm,avs-tmon-bcm2838";
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+ reg = <0x7d5d2200 0x2c>;
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+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "tmon";
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+ clocks = <&clocks BCM2835_CLOCK_TSENS>;
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+ #thermal-sensor-cells = <0>;
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+ status = "okay";
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+ };
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+
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+ pm: watchdog@7e100000 {
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+ reg = <0x7e100000 0x114>,
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+ <0x7e00a000 0x24>,
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+ <0x7ec11000 0x20>;
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+ };
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+
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+ rng@7e104000 {
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+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+
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+ uart2: serial@7e201400 {
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+ compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
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+ reg = <0x7e201400 0x200>;
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+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&clocks BCM2835_CLOCK_UART>,
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+ <&clocks BCM2835_CLOCK_VPU>;
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+ clock-names = "uartclk", "apb_pclk";
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+ arm,primecell-periphid = <0x00241011>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart3: serial@7e201600 {
|
|
+ compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
|
|
+ reg = <0x7e201600 0x200>;
|
|
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&clocks BCM2835_CLOCK_UART>,
|
|
+ <&clocks BCM2835_CLOCK_VPU>;
|
|
+ clock-names = "uartclk", "apb_pclk";
|
|
+ arm,primecell-periphid = <0x00241011>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart4: serial@7e201800 {
|
|
+ compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
|
|
+ reg = <0x7e201800 0x200>;
|
|
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&clocks BCM2835_CLOCK_UART>,
|
|
+ <&clocks BCM2835_CLOCK_VPU>;
|
|
+ clock-names = "uartclk", "apb_pclk";
|
|
+ arm,primecell-periphid = <0x00241011>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart5: serial@7e201a00 {
|
|
+ compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
|
|
+ reg = <0x7e201a00 0x200>;
|
|
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&clocks BCM2835_CLOCK_UART>,
|
|
+ <&clocks BCM2835_CLOCK_VPU>;
|
|
+ clock-names = "uartclk", "apb_pclk";
|
|
+ arm,primecell-periphid = <0x00241011>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ spi@7e204000 {
|
|
+ reg = <0x7e204000 0x0200>;
|
|
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ };
|
|
+
|
|
+ spi3: spi@7e204600 {
|
|
+ compatible = "brcm,bcm2835-spi";
|
|
+ reg = <0x7e204600 0x0200>;
|
|
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ spi4: spi@7e204800 {
|
|
+ compatible = "brcm,bcm2835-spi";
|
|
+ reg = <0x7e204800 0x0200>;
|
|
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ spi5: spi@7e204a00 {
|
|
+ compatible = "brcm,bcm2835-spi";
|
|
+ reg = <0x7e204a00 0x0200>;
|
|
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ spi6: spi@7e204c00 {
|
|
+ compatible = "brcm,bcm2835-spi";
|
|
+ reg = <0x7e204c00 0x0200>;
|
|
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c3: i2c@7e205600 {
|
|
+ compatible = "brcm,bcm2835-i2c";
|
|
+ reg = <0x7e205600 0x200>;
|
|
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c4: i2c@7e205800 {
|
|
+ compatible = "brcm,bcm2835-i2c";
|
|
+ reg = <0x7e205800 0x200>;
|
|
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c5: i2c@7e205a00 {
|
|
+ compatible = "brcm,bcm2835-i2c";
|
|
+ reg = <0x7e205a00 0x200>;
|
|
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c6: i2c@7e205c00 {
|
|
+ compatible = "brcm,bcm2835-i2c";
|
|
+ reg = <0x7e205c00 0x200>;
|
|
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pixelvalve@7e206000 {
|
|
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ };
|
|
+
|
|
+ pixelvalve@7e207000 {
|
|
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ };
|
|
+
|
|
+ emmc2: emmc2@7e340000 {
|
|
+ compatible = "brcm,bcm2711-emmc2";
|
|
+ status = "okay";
|
|
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&clocks BCM2838_CLOCK_EMMC2>;
|
|
+ reg = <0x7e340000 0x100>;
|
|
+ };
|
|
+
|
|
+ hvs@7e400000 {
|
|
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ };
|
|
+
|
|
+ pixelvalve@7e807000 {
|
|
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ arm-pmu {
|
|
+ /*
|
|
+ * N.B. the A72 PMU support only exists in arch/arm64, hence
|
|
+ * the fallback to the A53 version.
|
|
+ */
|
|
+ compatible = "arm,cortex-a72-pmu", "arm,cortex-a53-pmu";
|
|
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ };
|
|
+
|
|
+ timer {
|
|
+ compatible = "arm,armv7-timer";
|
|
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
|
|
+ IRQ_TYPE_LEVEL_LOW)>,
|
|
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
|
|
+ IRQ_TYPE_LEVEL_LOW)>,
|
|
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
|
|
+ IRQ_TYPE_LEVEL_LOW)>,
|
|
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
|
|
+ IRQ_TYPE_LEVEL_LOW)>;
|
|
+ arm,cpu-registers-not-fw-configured;
|
|
+ always-on;
|
|
+ };
|
|
+
|
|
+ cpus: cpus {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
|
|
+
|
|
+ cpu0: cpu@0 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a72";
|
|
+ reg = <0>;
|
|
+ enable-method = "spin-table";
|
|
+ cpu-release-addr = <0x0 0x000000d8>;
|
|
+ };
|
|
+
|
|
+ cpu1: cpu@1 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a72";
|
|
+ reg = <1>;
|
|
+ enable-method = "spin-table";
|
|
+ cpu-release-addr = <0x0 0x000000e0>;
|
|
+ };
|
|
+
|
|
+ cpu2: cpu@2 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a72";
|
|
+ reg = <2>;
|
|
+ enable-method = "spin-table";
|
|
+ cpu-release-addr = <0x0 0x000000e8>;
|
|
+ };
|
|
+
|
|
+ cpu3: cpu@3 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a72";
|
|
+ reg = <3>;
|
|
+ enable-method = "spin-table";
|
|
+ cpu-release-addr = <0x0 0x000000f0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ v3dbus {
|
|
+ compatible = "simple-bus";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges = <0x7c500000 0x0 0xfc500000 0x03300000>,
|
|
+ <0x40000000 0x0 0xff800000 0x00800000>;
|
|
+ dma-ranges = <0x00000000 0x0 0x00000000 0x3c000000>;
|
|
+
|
|
+ v3d: v3d@7ec04000 {
|
|
+ compatible = "brcm,2711-v3d";
|
|
+ reg =
|
|
+ <0x7ec00000 0x4000>,
|
|
+ <0x7ec04000 0x4000>;
|
|
+ reg-names = "hub", "core0";
|
|
+
|
|
+ power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
|
|
+ resets = <&pm BCM2835_RESET_V3D>;
|
|
+ clocks = <&clocks BCM2835_CLOCK_V3D>;
|
|
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ scb: scb {
|
|
+ compatible = "simple-bus";
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <1>;
|
|
+
|
|
+ ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
|
|
+ <0x0 0x40000000 0x0 0xff800000 0x00800000>,
|
|
+ <0x6 0x00000000 0x6 0x00000000 0x40000000>,
|
|
+ <0x0 0x00000000 0x0 0x00000000 0xfc000000>;
|
|
+ dma-ranges = <0x0 0x00000000 0x0 0x00000000 0xfc000000>;
|
|
+
|
|
+ pcie_0: pcie@7d500000 {
|
|
+ reg = <0x0 0x7d500000 0x9310>,
|
|
+ <0x0 0x7e00f300 0x20>;
|
|
+ msi-controller;
|
|
+ msi-parent = <&pcie_0>;
|
|
+ #address-cells = <3>;
|
|
+ #interrupt-cells = <1>;
|
|
+ #size-cells = <2>;
|
|
+ bus-range = <0x0 0x01>;
|
|
+ compatible = "brcm,bcm7211-pcie", "brcm,bcm7445-pcie",
|
|
+ "brcm,pci-plat-dev";
|
|
+ max-link-speed = <2>;
|
|
+ tot-num-pcie = <1>;
|
|
+ linux,pci-domain = <0>;
|
|
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "pcie", "msi";
|
|
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
|
+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
|
|
+ IRQ_TYPE_LEVEL_HIGH
|
|
+ 0 0 0 2 &gicv2 GIC_SPI 144
|
|
+ IRQ_TYPE_LEVEL_HIGH
|
|
+ 0 0 0 3 &gicv2 GIC_SPI 145
|
|
+ IRQ_TYPE_LEVEL_HIGH
|
|
+ 0 0 0 4 &gicv2 GIC_SPI 146
|
|
+ IRQ_TYPE_LEVEL_HIGH>;
|
|
+
|
|
+ /* Map outbound accesses from scb:0x6_00000000-03ffffff
|
|
+ * to pci:0x0_f8000000-fbffffff
|
|
+ */
|
|
+ ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
|
|
+ 0x0 0x04000000>;
|
|
+ /* Map inbound accesses from pci:0x0_00000000..ffffffff
|
|
+ * to scb:0x0_00000000-ffffffff
|
|
+ */
|
|
+ dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
|
|
+ 0x1 0x00000000>;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ genet: genet@7d580000 {
|
|
+ compatible = "brcm,genet-v5";
|
|
+ reg = <0x0 0x7d580000 0x10000>;
|
|
+ status = "okay";
|
|
+ #address-cells = <0x1>;
|
|
+ #size-cells = <0x1>;
|
|
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ phy-handle = <&phy1>;
|
|
+ phy-mode = "rgmii";
|
|
+ mdio@e14 {
|
|
+ #address-cells = <0x0>;
|
|
+ #size-cells = <0x1>;
|
|
+ compatible = "brcm,genet-mdio-v5";
|
|
+ reg = <0xe14 0x8>;
|
|
+ reg-names = "mdio";
|
|
+ phy1: genet-phy@0 {
|
|
+ compatible =
|
|
+ "ethernet-phy-ieee802.3-c22";
|
|
+ /* No interrupts - use PHY_POLL */
|
|
+ max-speed = <1000>;
|
|
+ reg = <0x1>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ xhci: xhci@7e9c0000 {
|
|
+ compatible = "generic-xhci";
|
|
+ status = "disabled";
|
|
+ reg = <0x0 0x7e9c0000 0x100000>;
|
|
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ };
|
|
+
|
|
+ vchiq: mailbox@7e00b840 {
|
|
+ compatible = "brcm,bcm2838-vchiq";
|
|
+ reg = <0 0x7e00b840 0x3c>;
|
|
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ };
|
|
+
|
|
+ hevc-decoder@7eb00000 {
|
|
+ compatible = "raspberrypi,argon-hevc-decoder";
|
|
+ reg = <0x0 0x7eb00000 0x10000>;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ argon-local-intc@7eb10000 {
|
|
+ compatible = "raspberrypi,argon-local-intc";
|
|
+ reg = <0x0 0x7eb10000 0x1000>;
|
|
+ status = "okay";
|
|
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ };
|
|
+
|
|
+ h264-decoder@7eb20000 {
|
|
+ compatible = "raspberrypi,argon-h264-decoder";
|
|
+ reg = <0x0 0x7eb20000 0x10000>;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ vp9-decoder@7eb30000 {
|
|
+ compatible = "raspberrypi,argon-vp9-decoder";
|
|
+ reg = <0x0 0x7eb30000 0x10000>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&clk_osc {
|
|
+ clock-frequency = <54000000>;
|
|
+};
|
|
+
|
|
+&clocks {
|
|
+ compatible = "brcm,bcm2838-cprman";
|
|
+};
|
|
+
|
|
+&cpu_thermal {
|
|
+ coefficients = <(-487) 410040>;
|
|
+};
|
|
+
|
|
+&dsi0 {
|
|
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
+};
|
|
+
|
|
+&dsi1 {
|
|
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
+};
|
|
+
|
|
+&gpio {
|
|
+ gpclk0_gpio49: gpclk0_gpio49 {
|
|
+ brcm,pins = <49>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT1>;
|
|
+ brcm,pull = <BCM2835_PUD_OFF>;
|
|
+ };
|
|
+ gpclk1_gpio50: gpclk1_gpio50 {
|
|
+ brcm,pins = <50>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT1>;
|
|
+ brcm,pull = <BCM2835_PUD_OFF>;
|
|
+ };
|
|
+ gpclk2_gpio51: gpclk2_gpio51 {
|
|
+ brcm,pins = <51>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT1>;
|
|
+ brcm,pull = <BCM2835_PUD_OFF>;
|
|
+ };
|
|
+
|
|
+ i2c0_gpio46: i2c0_gpio46 {
|
|
+ brcm,pins = <46 47>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT0>;
|
|
+ };
|
|
+ i2c1_gpio46: i2c1_gpio46 {
|
|
+ brcm,pins = <46 47>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT1>;
|
|
+ };
|
|
+ i2c3_gpio2: i2c3_gpio2 {
|
|
+ brcm,pins = <2 3>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT5>;
|
|
+ };
|
|
+ i2c3_gpio4: i2c3_gpio4 {
|
|
+ brcm,pins = <4 5>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT5>;
|
|
+ };
|
|
+ i2c4_gpio6: i2c4_gpio6 {
|
|
+ brcm,pins = <6 7>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT5>;
|
|
+ };
|
|
+ i2c4_gpio8: i2c4_gpio8 {
|
|
+ brcm,pins = <8 9>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT5>;
|
|
+ };
|
|
+ i2c5_gpio10: i2c5_gpio10 {
|
|
+ brcm,pins = <10 11>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT5>;
|
|
+ };
|
|
+ i2c5_gpio12: i2c5_gpio12 {
|
|
+ brcm,pins = <12 13>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT5>;
|
|
+ };
|
|
+ i2c6_gpio0: i2c6_gpio0 {
|
|
+ brcm,pins = <0 1>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT5>;
|
|
+ };
|
|
+ i2c6_gpio22: i2c6_gpio22 {
|
|
+ brcm,pins = <22 23>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT5>;
|
|
+ };
|
|
+ i2c_slave_gpio8: i2c_slave_gpio8 {
|
|
+ brcm,pins = <8 9 10 11>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT3>;
|
|
+ };
|
|
+
|
|
+ jtag_gpio48: jtag_gpio48 {
|
|
+ brcm,pins = <48 49 50 51 52 53>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT4>;
|
|
+ };
|
|
+
|
|
+ mii_gpio28: mii_gpio28 {
|
|
+ brcm,pins = <28 29 30 31>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT4>;
|
|
+ };
|
|
+ mii_gpio36: mii_gpio36 {
|
|
+ brcm,pins = <36 37 38 39>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT5>;
|
|
+ };
|
|
+
|
|
+ pcm_gpio50: pcm_gpio50 {
|
|
+ brcm,pins = <50 51 52 53>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT2>;
|
|
+ };
|
|
+
|
|
+ pwm0_gpio52: pwm0_gpio52 {
|
|
+ brcm,pins = <52>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT1>;
|
|
+ brcm,pull = <BCM2835_PUD_OFF>;
|
|
+ };
|
|
+ pwm1_gpio53: pwm1_gpio53 {
|
|
+ brcm,pins = <53>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT1>;
|
|
+ brcm,pull = <BCM2835_PUD_OFF>;
|
|
+ };
|
|
+
|
|
+ /* The following group consists of:
|
|
+ * RGMII_START_STOP
|
|
+ * RGMII_RX_OK
|
|
+ */
|
|
+ rgmii_gpio35: rgmii_gpio35 {
|
|
+ brcm,pins = <35 36>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT4>;
|
|
+ };
|
|
+ rgmii_irq_gpio34: rgmii_irq_gpio34 {
|
|
+ brcm,pins = <34>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT5>;
|
|
+ };
|
|
+ rgmii_irq_gpio39: rgmii_irq_gpio39 {
|
|
+ brcm,pins = <39>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT4>;
|
|
+ };
|
|
+ rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
|
|
+ brcm,pins = <28 29>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT5>;
|
|
+ };
|
|
+ rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
|
|
+ brcm,pins = <37 38>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT4>;
|
|
+ };
|
|
+
|
|
+ spi0_gpio46: spi0_gpio46 {
|
|
+ brcm,pins = <46 47 48 49>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT2>;
|
|
+ };
|
|
+ spi2_gpio46: spi2_gpio46 {
|
|
+ brcm,pins = <46 47 48 49 50>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT5>;
|
|
+ };
|
|
+ spi3_gpio0: spi3_gpio0 {
|
|
+ brcm,pins = <0 1 2 3>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT3>;
|
|
+ };
|
|
+ spi4_gpio4: spi4_gpio4 {
|
|
+ brcm,pins = <4 5 6 7>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT3>;
|
|
+ };
|
|
+ spi5_gpio12: spi5_gpio12 {
|
|
+ brcm,pins = <12 13 14 15>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT3>;
|
|
+ };
|
|
+ spi6_gpio18: spi6_gpio18 {
|
|
+ brcm,pins = <18 19 20 21>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT3>;
|
|
+ };
|
|
+
|
|
+ uart2_gpio0: uart2_gpio0 {
|
|
+ brcm,pins = <0 1>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT4>;
|
|
+ brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
|
|
+ };
|
|
+ uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
|
|
+ brcm,pins = <2 3>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT4>;
|
|
+ brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
|
|
+ };
|
|
+ uart3_gpio4: uart3_gpio4 {
|
|
+ brcm,pins = <4 5>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT4>;
|
|
+ brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
|
|
+ };
|
|
+ uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
|
|
+ brcm,pins = <6 7>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT4>;
|
|
+ brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
|
|
+ };
|
|
+ uart4_gpio8: uart4_gpio8 {
|
|
+ brcm,pins = <8 9>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT4>;
|
|
+ brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
|
|
+ };
|
|
+ uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
|
|
+ brcm,pins = <10 11>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT4>;
|
|
+ brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
|
|
+ };
|
|
+ uart5_gpio12: uart5_gpio12 {
|
|
+ brcm,pins = <12 13>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT4>;
|
|
+ brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
|
|
+ };
|
|
+ uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
|
|
+ brcm,pins = <14 15>;
|
|
+ brcm,function = <BCM2835_FSEL_ALT4>;
|
|
+ brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&vec {
|
|
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
|
+};
|
|
+
|
|
+&usb {
|
|
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
+};
|
|
+
|
|
+&hdmi {
|
|
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
+};
|
|
+
|
|
+&uart1 {
|
|
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
+};
|
|
+
|
|
+&spi1 {
|
|
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
+};
|
|
+
|
|
+&spi2 {
|
|
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
+};
|
|
+
|
|
+&csi0 {
|
|
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
|
+};
|
|
+
|
|
+&csi1 {
|
|
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
+};
|
|
+
|
|
+&sdhci {
|
|
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
|
+};
|
|
+
|
|
+&i2c0 {
|
|
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
+};
|
|
+
|
|
+&i2c1 {
|
|
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
+};
|
|
+
|
|
+&i2c2 {
|
|
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
+};
|
|
+
|
|
+&gpio {
|
|
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
+};
|
|
+
|
|
+&mailbox {
|
|
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
+};
|
|
+
|
|
+&rng {
|
|
+ compatible = "brcm,bcm2838-rng200";
|
|
+};
|
|
+
|
|
+&sdhost {
|
|
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
|
+};
|
|
+
|
|
+&uart0 {
|
|
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
+};
|
|
+
|
|
+&dma {
|
|
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 7 */
|
|
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 8 */
|
|
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 9 */
|
|
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 10 */
|
|
+ /* DMA4 - 40 bit DMA engines */
|
|
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, /* dma4 11 */
|
|
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, /* dma4 12 */
|
|
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, /* dma4 13 */
|
|
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; /* dma4 14 */
|
|
+ interrupt-names = "dma0",
|
|
+ "dma1",
|
|
+ "dma2",
|
|
+ "dma3",
|
|
+ "dma4",
|
|
+ "dma5",
|
|
+ "dma6",
|
|
+ "dma7",
|
|
+ "dma8",
|
|
+ "dma9",
|
|
+ "dma10",
|
|
+ "dma11",
|
|
+ "dma12",
|
|
+ "dma13",
|
|
+ "dma14";
|
|
+ brcm,dma-channel-mask = <0x7ef5>;
|
|
+};
|