mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 22:23:27 +00:00
516 lines
14 KiB
Diff
516 lines
14 KiB
Diff
From 318d93bc41823e86967c8251eef0444a72e4d687 Mon Sep 17 00:00:00 2001
|
|
From: Jens Kuske <jenskuske@gmail.com>
|
|
Date: Fri, 4 Dec 2015 22:24:42 +0100
|
|
Subject: [PATCH] ARM: dts: sunxi: Add Allwinner H3 DTSI
|
|
|
|
The Allwinner H3 is a home entertainment system oriented SoC with
|
|
four Cortex-A7 cores and a Mali-400MP2 GPU.
|
|
|
|
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
|
|
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
---
|
|
arch/arm/boot/dts/sun8i-h3.dtsi | 497 ++++++++++++++++++++++++++++++++++++++++
|
|
1 file changed, 497 insertions(+)
|
|
create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi
|
|
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
|
|
@@ -0,0 +1,497 @@
|
|
+/*
|
|
+ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
|
|
+ *
|
|
+ * This file is dual-licensed: you can use it either under the terms
|
|
+ * of the GPL or the X11 license, at your option. Note that this dual
|
|
+ * licensing only applies to this file, and not this project as a
|
|
+ * whole.
|
|
+ *
|
|
+ * a) This file is free software; you can redistribute it and/or
|
|
+ * modify it under the terms of the GNU General Public License as
|
|
+ * published by the Free Software Foundation; either version 2 of the
|
|
+ * License, or (at your option) any later version.
|
|
+ *
|
|
+ * This file is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * Or, alternatively,
|
|
+ *
|
|
+ * b) Permission is hereby granted, free of charge, to any person
|
|
+ * obtaining a copy of this software and associated documentation
|
|
+ * files (the "Software"), to deal in the Software without
|
|
+ * restriction, including without limitation the rights to use,
|
|
+ * copy, modify, merge, publish, distribute, sublicense, and/or
|
|
+ * sell copies of the Software, and to permit persons to whom the
|
|
+ * Software is furnished to do so, subject to the following
|
|
+ * conditions:
|
|
+ *
|
|
+ * The above copyright notice and this permission notice shall be
|
|
+ * included in all copies or substantial portions of the Software.
|
|
+ *
|
|
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
|
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
|
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
|
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
|
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
+ * OTHER DEALINGS IN THE SOFTWARE.
|
|
+ */
|
|
+
|
|
+#include "skeleton.dtsi"
|
|
+
|
|
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
+#include <dt-bindings/pinctrl/sun4i-a10.h>
|
|
+
|
|
+/ {
|
|
+ interrupt-parent = <&gic>;
|
|
+
|
|
+ cpus {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ cpu@0 {
|
|
+ compatible = "arm,cortex-a7";
|
|
+ device_type = "cpu";
|
|
+ reg = <0>;
|
|
+ };
|
|
+
|
|
+ cpu@1 {
|
|
+ compatible = "arm,cortex-a7";
|
|
+ device_type = "cpu";
|
|
+ reg = <1>;
|
|
+ };
|
|
+
|
|
+ cpu@2 {
|
|
+ compatible = "arm,cortex-a7";
|
|
+ device_type = "cpu";
|
|
+ reg = <2>;
|
|
+ };
|
|
+
|
|
+ cpu@3 {
|
|
+ compatible = "arm,cortex-a7";
|
|
+ device_type = "cpu";
|
|
+ reg = <3>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ timer {
|
|
+ compatible = "arm,armv7-timer";
|
|
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
+ };
|
|
+
|
|
+ clocks {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges;
|
|
+
|
|
+ osc24M: osc24M_clk {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <24000000>;
|
|
+ clock-output-names = "osc24M";
|
|
+ };
|
|
+
|
|
+ osc32k: osc32k_clk {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <32768>;
|
|
+ clock-output-names = "osc32k";
|
|
+ };
|
|
+
|
|
+ pll1: clk@01c20000 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun8i-a23-pll1-clk";
|
|
+ reg = <0x01c20000 0x4>;
|
|
+ clocks = <&osc24M>;
|
|
+ clock-output-names = "pll1";
|
|
+ };
|
|
+
|
|
+ /* dummy clock until actually implemented */
|
|
+ pll5: pll5_clk {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <0>;
|
|
+ clock-output-names = "pll5";
|
|
+ };
|
|
+
|
|
+ pll6: clk@01c20028 {
|
|
+ #clock-cells = <1>;
|
|
+ compatible = "allwinner,sun6i-a31-pll6-clk";
|
|
+ reg = <0x01c20028 0x4>;
|
|
+ clocks = <&osc24M>;
|
|
+ clock-output-names = "pll6", "pll6x2";
|
|
+ };
|
|
+
|
|
+ pll6d2: pll6d2_clk {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-factor-clock";
|
|
+ clock-div = <2>;
|
|
+ clock-mult = <1>;
|
|
+ clocks = <&pll6 0>;
|
|
+ clock-output-names = "pll6d2";
|
|
+ };
|
|
+
|
|
+ /* dummy clock until pll6 can be reused */
|
|
+ pll8: pll8_clk {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <1>;
|
|
+ clock-output-names = "pll8";
|
|
+ };
|
|
+
|
|
+ cpu: cpu_clk@01c20050 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-a10-cpu-clk";
|
|
+ reg = <0x01c20050 0x4>;
|
|
+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
|
|
+ clock-output-names = "cpu";
|
|
+ };
|
|
+
|
|
+ axi: axi_clk@01c20050 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-a10-axi-clk";
|
|
+ reg = <0x01c20050 0x4>;
|
|
+ clocks = <&cpu>;
|
|
+ clock-output-names = "axi";
|
|
+ };
|
|
+
|
|
+ ahb1: ahb1_clk@01c20054 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun6i-a31-ahb1-clk";
|
|
+ reg = <0x01c20054 0x4>;
|
|
+ clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
|
|
+ clock-output-names = "ahb1";
|
|
+ };
|
|
+
|
|
+ ahb2: ahb2_clk@01c2005c {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun8i-h3-ahb2-clk";
|
|
+ reg = <0x01c2005c 0x4>;
|
|
+ clocks = <&ahb1>, <&pll6d2>;
|
|
+ clock-output-names = "ahb2";
|
|
+ };
|
|
+
|
|
+ apb1: apb1_clk@01c20054 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-a10-apb0-clk";
|
|
+ reg = <0x01c20054 0x4>;
|
|
+ clocks = <&ahb1>;
|
|
+ clock-output-names = "apb1";
|
|
+ };
|
|
+
|
|
+ apb2: apb2_clk@01c20058 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun4i-a10-apb1-clk";
|
|
+ reg = <0x01c20058 0x4>;
|
|
+ clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
|
|
+ clock-output-names = "apb2";
|
|
+ };
|
|
+
|
|
+ bus_gates: clk@01c20060 {
|
|
+ #clock-cells = <1>;
|
|
+ compatible = "allwinner,sun8i-h3-bus-gates-clk";
|
|
+ reg = <0x01c20060 0x14>;
|
|
+ clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
|
|
+ clock-names = "ahb1", "ahb2", "apb1", "apb2";
|
|
+ clock-indices = <5>, <6>, <8>,
|
|
+ <9>, <10>, <13>,
|
|
+ <14>, <17>, <18>,
|
|
+ <19>, <20>,
|
|
+ <21>, <23>,
|
|
+ <24>, <25>,
|
|
+ <26>, <27>,
|
|
+ <28>, <29>,
|
|
+ <30>, <31>, <32>,
|
|
+ <35>, <36>, <37>,
|
|
+ <40>, <41>, <43>,
|
|
+ <44>, <52>, <53>,
|
|
+ <54>, <64>,
|
|
+ <65>, <69>, <72>,
|
|
+ <76>, <77>, <78>,
|
|
+ <96>, <97>, <98>,
|
|
+ <112>, <113>,
|
|
+ <114>, <115>,
|
|
+ <116>, <128>, <135>;
|
|
+ clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
|
|
+ "bus_mmc1", "bus_mmc2", "bus_nand",
|
|
+ "bus_sdram", "bus_gmac", "bus_ts",
|
|
+ "bus_hstimer", "bus_spi0",
|
|
+ "bus_spi1", "bus_otg",
|
|
+ "bus_otg_ehci0", "bus_ehci1",
|
|
+ "bus_ehci2", "bus_ehci3",
|
|
+ "bus_otg_ohci0", "bus_ohci1",
|
|
+ "bus_ohci2", "bus_ohci3", "bus_ve",
|
|
+ "bus_lcd0", "bus_lcd1", "bus_deint",
|
|
+ "bus_csi", "bus_tve", "bus_hdmi",
|
|
+ "bus_de", "bus_gpu", "bus_msgbox",
|
|
+ "bus_spinlock", "bus_codec",
|
|
+ "bus_spdif", "bus_pio", "bus_ths",
|
|
+ "bus_i2s0", "bus_i2s1", "bus_i2s2",
|
|
+ "bus_i2c0", "bus_i2c1", "bus_i2c2",
|
|
+ "bus_uart0", "bus_uart1",
|
|
+ "bus_uart2", "bus_uart3",
|
|
+ "bus_scr", "bus_ephy", "bus_dbg";
|
|
+ };
|
|
+
|
|
+ mmc0_clk: clk@01c20088 {
|
|
+ #clock-cells = <1>;
|
|
+ compatible = "allwinner,sun4i-a10-mmc-clk";
|
|
+ reg = <0x01c20088 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 0>, <&pll8>;
|
|
+ clock-output-names = "mmc0",
|
|
+ "mmc0_output",
|
|
+ "mmc0_sample";
|
|
+ };
|
|
+
|
|
+ mmc1_clk: clk@01c2008c {
|
|
+ #clock-cells = <1>;
|
|
+ compatible = "allwinner,sun4i-a10-mmc-clk";
|
|
+ reg = <0x01c2008c 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 0>, <&pll8>;
|
|
+ clock-output-names = "mmc1",
|
|
+ "mmc1_output",
|
|
+ "mmc1_sample";
|
|
+ };
|
|
+
|
|
+ mmc2_clk: clk@01c20090 {
|
|
+ #clock-cells = <1>;
|
|
+ compatible = "allwinner,sun4i-a10-mmc-clk";
|
|
+ reg = <0x01c20090 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 0>, <&pll8>;
|
|
+ clock-output-names = "mmc2",
|
|
+ "mmc2_output",
|
|
+ "mmc2_sample";
|
|
+ };
|
|
+
|
|
+ mbus_clk: clk@01c2015c {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun8i-a23-mbus-clk";
|
|
+ reg = <0x01c2015c 0x4>;
|
|
+ clocks = <&osc24M>, <&pll6 1>, <&pll5>;
|
|
+ clock-output-names = "mbus";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ soc {
|
|
+ compatible = "simple-bus";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges;
|
|
+
|
|
+ dma: dma-controller@01c02000 {
|
|
+ compatible = "allwinner,sun8i-h3-dma";
|
|
+ reg = <0x01c02000 0x1000>;
|
|
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&bus_gates 6>;
|
|
+ resets = <&ahb_rst 6>;
|
|
+ #dma-cells = <1>;
|
|
+ };
|
|
+
|
|
+ mmc0: mmc@01c0f000 {
|
|
+ compatible = "allwinner,sun5i-a13-mmc";
|
|
+ reg = <0x01c0f000 0x1000>;
|
|
+ clocks = <&bus_gates 8>,
|
|
+ <&mmc0_clk 0>,
|
|
+ <&mmc0_clk 1>,
|
|
+ <&mmc0_clk 2>;
|
|
+ clock-names = "ahb",
|
|
+ "mmc",
|
|
+ "output",
|
|
+ "sample";
|
|
+ resets = <&ahb_rst 8>;
|
|
+ reset-names = "ahb";
|
|
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ mmc1: mmc@01c10000 {
|
|
+ compatible = "allwinner,sun5i-a13-mmc";
|
|
+ reg = <0x01c10000 0x1000>;
|
|
+ clocks = <&bus_gates 9>,
|
|
+ <&mmc1_clk 0>,
|
|
+ <&mmc1_clk 1>,
|
|
+ <&mmc1_clk 2>;
|
|
+ clock-names = "ahb",
|
|
+ "mmc",
|
|
+ "output",
|
|
+ "sample";
|
|
+ resets = <&ahb_rst 9>;
|
|
+ reset-names = "ahb";
|
|
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ mmc2: mmc@01c11000 {
|
|
+ compatible = "allwinner,sun5i-a13-mmc";
|
|
+ reg = <0x01c11000 0x1000>;
|
|
+ clocks = <&bus_gates 10>,
|
|
+ <&mmc2_clk 0>,
|
|
+ <&mmc2_clk 1>,
|
|
+ <&mmc2_clk 2>;
|
|
+ clock-names = "ahb",
|
|
+ "mmc",
|
|
+ "output",
|
|
+ "sample";
|
|
+ resets = <&ahb_rst 10>;
|
|
+ reset-names = "ahb";
|
|
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ pio: pinctrl@01c20800 {
|
|
+ compatible = "allwinner,sun8i-h3-pinctrl";
|
|
+ reg = <0x01c20800 0x400>;
|
|
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&bus_gates 69>;
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <3>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+
|
|
+ uart0_pins_a: uart0@0 {
|
|
+ allwinner,pins = "PA4", "PA5";
|
|
+ allwinner,function = "uart0";
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
+ };
|
|
+
|
|
+ mmc0_pins_a: mmc0@0 {
|
|
+ allwinner,pins = "PF0", "PF1", "PF2", "PF3",
|
|
+ "PF4", "PF5";
|
|
+ allwinner,function = "mmc0";
|
|
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
+ };
|
|
+
|
|
+ mmc0_cd_pin: mmc0_cd_pin@0 {
|
|
+ allwinner,pins = "PF6";
|
|
+ allwinner,function = "gpio_in";
|
|
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
|
+ };
|
|
+
|
|
+ mmc1_pins_a: mmc1@0 {
|
|
+ allwinner,pins = "PG0", "PG1", "PG2", "PG3",
|
|
+ "PG4", "PG5";
|
|
+ allwinner,function = "mmc1";
|
|
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ahb_rst: reset@01c202c0 {
|
|
+ #reset-cells = <1>;
|
|
+ compatible = "allwinner,sun6i-a31-ahb1-reset";
|
|
+ reg = <0x01c202c0 0xc>;
|
|
+ };
|
|
+
|
|
+ apb1_rst: reset@01c202d0 {
|
|
+ #reset-cells = <1>;
|
|
+ compatible = "allwinner,sun6i-a31-clock-reset";
|
|
+ reg = <0x01c202d0 0x4>;
|
|
+ };
|
|
+
|
|
+ apb2_rst: reset@01c202d8 {
|
|
+ #reset-cells = <1>;
|
|
+ compatible = "allwinner,sun6i-a31-clock-reset";
|
|
+ reg = <0x01c202d8 0x4>;
|
|
+ };
|
|
+
|
|
+ timer@01c20c00 {
|
|
+ compatible = "allwinner,sun4i-a10-timer";
|
|
+ reg = <0x01c20c00 0xa0>;
|
|
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&osc24M>;
|
|
+ };
|
|
+
|
|
+ wdt0: watchdog@01c20ca0 {
|
|
+ compatible = "allwinner,sun6i-a31-wdt";
|
|
+ reg = <0x01c20ca0 0x20>;
|
|
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ };
|
|
+
|
|
+ uart0: serial@01c28000 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x01c28000 0x400>;
|
|
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&bus_gates 112>;
|
|
+ resets = <&apb2_rst 16>;
|
|
+ dmas = <&dma 6>, <&dma 6>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart1: serial@01c28400 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x01c28400 0x400>;
|
|
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&bus_gates 113>;
|
|
+ resets = <&apb2_rst 17>;
|
|
+ dmas = <&dma 7>, <&dma 7>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart2: serial@01c28800 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x01c28800 0x400>;
|
|
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&bus_gates 114>;
|
|
+ resets = <&apb2_rst 18>;
|
|
+ dmas = <&dma 8>, <&dma 8>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart3: serial@01c28c00 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x01c28c00 0x400>;
|
|
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&bus_gates 115>;
|
|
+ resets = <&apb2_rst 19>;
|
|
+ dmas = <&dma 9>, <&dma 9>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gic: interrupt-controller@01c81000 {
|
|
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
|
|
+ reg = <0x01c81000 0x1000>,
|
|
+ <0x01c82000 0x1000>,
|
|
+ <0x01c84000 0x2000>,
|
|
+ <0x01c86000 0x2000>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <3>;
|
|
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
+ };
|
|
+
|
|
+ rtc: rtc@01f00000 {
|
|
+ compatible = "allwinner,sun6i-a31-rtc";
|
|
+ reg = <0x01f00000 0x54>;
|
|
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ };
|
|
+ };
|
|
+};
|