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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
55 lines
1.6 KiB
Diff
55 lines
1.6 KiB
Diff
From a3f36600fd758173c1ec315684e4ae72c6e85654 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Fri, 8 Jul 2022 15:38:45 +0200
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Subject: [PATCH] arm64: dts: qcom: ipq8074: add #size/address-cells to DTSI
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Add #size-cells and #address-cells to the SoC DTSI to avoid duplicating
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the same properties in board DTS files.
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Remove the mentioned properties from current board DTS files.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20220708133846.599735-1-robimarko@gmail.com
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---
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arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 --
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arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 3 ---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 +++
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3 files changed, 3 insertions(+), 5 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
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+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
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@@ -5,8 +5,6 @@
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#include "ipq8074.dtsi"
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/ {
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- #address-cells = <0x2>;
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- #size-cells = <0x2>;
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model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
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compatible = "qcom,ipq8074-hk01", "qcom,ipq8074";
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interrupt-parent = <&intc>;
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--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
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@@ -7,9 +7,6 @@
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#include "ipq8074.dtsi"
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/ {
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- #address-cells = <0x2>;
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- #size-cells = <0x2>;
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-
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interrupt-parent = <&intc>;
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aliases {
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -7,6 +7,9 @@
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#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
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/ {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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model = "Qualcomm Technologies, Inc. IPQ8074";
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compatible = "qcom,ipq8074";
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