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https://github.com/openwrt/openwrt.git
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863e79f8d5
The following patches were dropped because they are already applied upstream: 0012-pinctrl-lantiq-fix-up-pinmux.patch 0013-MTD-lantiq-xway-fix-invalid-operator.patch 0014-MTD-lantiq-xway-the-latched-command-should-be-persis.patch 0015-MTD-lantiq-xway-remove-endless-loop.patch 0016-MTD-lantiq-xway-add-missing-write_buf-and-read_buf-t.patch 0017-MTD-xway-fix-nand-locking.patch 0044-pinctrl-lantiq-introduce-new-dedicated-devicetree-bi.patch 0045-pinctrl-lantiq-Fix-GPIO-Setup-of-GPIO-Port3.patch 0046-pinctrl-lantiq-2-pins-have-the-wrong-mux-list.patch 0047-irq-fixes.patch 0047-mtd-plat-nand-pass-of-node.patch 0060-usb-dwc2-Add-support-for-Lantiq-ARX-and-XRX-SoCs.patch 0120-MIPS-lantiq-add-support-for-device-tree-file-from-bo.patch 0121-MIPS-lantiq-make-it-possible-to-build-in-no-device-t.patch 122-MIPS-store-the-appended-dtb-address-in-a-variable.patch The PHY driver was reduced to the code adding the LED configuration, the rest is already upstream: 0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch The SPI driver was replaced with the version pending for upstream inclusion: New driver: 0090-spi-add-transfer_status-callback.patch 0091-spi-lantiq-ssc-add-support-for-Lantiq-SSC-SPI-controller.patch Old driver: 0100-spi-add-support-for-Lantiq-SPI-controller.patch Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
209 lines
5.3 KiB
Diff
209 lines
5.3 KiB
Diff
--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -2310,6 +2310,12 @@ config MIPS_VPE_LOADER
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Includes a loader for loading an elf relocatable object
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onto another VPE and running it.
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+config IFX_VPE_EXT
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+ bool "IFX APRP Extensions"
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+ depends on MIPS_VPE_LOADER
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+ help
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+ IFX included extensions in APRP
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+
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config MIPS_VPE_LOADER_CMP
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bool
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default "y"
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--- a/arch/mips/include/asm/vpe.h
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+++ b/arch/mips/include/asm/vpe.h
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@@ -127,4 +127,23 @@ void cleanup_tc(struct tc *tc);
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int __init vpe_module_init(void);
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void __exit vpe_module_exit(void);
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+
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+/* For the explanation of the APIs please refer the section "MT APRP Kernel
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+ * Programming" in AR9 SW Architecture Specification
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+ */
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+int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags);
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+int32_t vpe1_sw_stop(uint32_t flags);
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+uint32_t vpe1_get_load_addr(uint32_t flags);
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+uint32_t vpe1_get_max_mem(uint32_t flags);
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+
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+/* Watchdog APIs */
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+extern uint32_t vpe1_wdog_ctr;
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+extern uint32_t vpe1_wdog_timeout;
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+
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+unsigned long vpe1_sw_wdog_start(unsigned long);
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+unsigned long vpe1_sw_wdog_stop(unsigned long);
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+
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+typedef int (*VPE_SW_WDOG_RESET)(unsigned long wdog_cleared_ok_count);
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+int32_t vpe1_sw_wdog_register_reset_handler(VPE_SW_WDOG_RESET reset_fn);
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+
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#endif /* _ASM_VPE_H */
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--- a/arch/mips/kernel/vpe-mt.c
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+++ b/arch/mips/kernel/vpe-mt.c
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@@ -29,6 +29,7 @@ int vpe_run(struct vpe *v)
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struct vpe_notifications *notifier;
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unsigned int vpeflags;
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struct tc *t;
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+ unsigned long physical_memsize = 0L;
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/* check we are the Master VPE */
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local_irq_save(flags);
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@@ -417,6 +418,8 @@ int __init vpe_module_init(void)
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}
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v->ntcs = hw_tcs - aprp_cpu_index();
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+ write_tc_c0_tcbind((read_tc_c0_tcbind() &
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+ ~TCBIND_CURVPE) | 1);
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/* add the tc to the list of this vpe's tc's. */
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list_add(&t->tc, &v->tc);
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@@ -519,3 +522,47 @@ void __exit vpe_module_exit(void)
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release_vpe(v);
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}
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}
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+
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+#ifdef CONFIG_IFX_VPE_EXT
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+int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags)
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+{
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+ enum vpe_state state;
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+ struct vpe *v = get_vpe(tclimit);
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+ struct vpe_notifications *not;
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+
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+ if (tcmask || flags) {
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+ pr_warn("Currently tcmask and flags should be 0. Other values are not supported\n");
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+ return -1;
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+ }
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+
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+ state = xchg(&v->state, VPE_STATE_INUSE);
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+ if (state != VPE_STATE_UNUSED) {
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+ vpe_stop(v);
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+
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+ list_for_each_entry(not, &v->notify, list) {
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+ not->stop(tclimit);
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+ }
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+ }
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+
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+ v->__start = (unsigned long)sw_start_addr;
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+
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+ if (!vpe_run(v)) {
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+ pr_debug("VPE loader: VPE1 running successfully\n");
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+ return 0;
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+ }
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+ return -1;
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+}
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+EXPORT_SYMBOL(vpe1_sw_start);
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+
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+int32_t vpe1_sw_stop(uint32_t flags)
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+{
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+ struct vpe *v = get_vpe(tclimit);
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+
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+ if (!vpe_free(v)) {
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+ pr_debug("RP Stopped\n");
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+ return 0;
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+ } else
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+ return -1;
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+}
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+EXPORT_SYMBOL(vpe1_sw_stop);
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+#endif
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--- a/arch/mips/kernel/vpe.c
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+++ b/arch/mips/kernel/vpe.c
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@@ -49,6 +49,59 @@ struct vpe_control vpecontrol = {
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.tc_list = LIST_HEAD_INIT(vpecontrol.tc_list)
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};
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+#ifdef CONFIG_IFX_VPE_EXT
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+unsigned int vpe1_load_addr;
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+
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+static int __init load_address(char *str)
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+{
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+ get_option(&str, &vpe1_load_addr);
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+ return 1;
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+}
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+__setup("vpe1_load_addr=", load_address);
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+
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+static unsigned int vpe1_mem;
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+static int __init vpe1mem(char *str)
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+{
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+ vpe1_mem = memparse(str, &str);
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+ return 1;
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+}
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+__setup("vpe1_mem=", vpe1mem);
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+
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+uint32_t vpe1_wdog_ctr;
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+static int __init wdog_ctr(char *str)
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+{
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+ get_option(&str, &vpe1_wdog_ctr);
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+ return 1;
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+}
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+EXPORT_SYMBOL(vpe1_wdog_ctr);
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+__setup("vpe1_wdog_ctr_addr=", wdog_ctr);
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+
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+uint32_t vpe1_wdog_timeout;
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+static int __init wdog_timeout(char *str)
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+{
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+ get_option(&str, &vpe1_wdog_timeout);
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+ return 1;
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+}
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+EXPORT_SYMBOL(vpe1_wdog_timeout);
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+__setup("vpe1_wdog_timeout=", wdog_timeout);
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+
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+uint32_t vpe1_get_load_addr(uint32_t flags)
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+{
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+ return vpe1_load_addr;
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+}
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+EXPORT_SYMBOL(vpe1_get_load_addr);
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+
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+uint32_t vpe1_get_max_mem(uint32_t flags)
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+{
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+ if (!vpe1_mem)
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+ return P_SIZE;
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+ else
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+ return vpe1_mem;
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+}
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+EXPORT_SYMBOL(vpe1_get_max_mem);
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+
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+#endif
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+
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/* get the vpe associated with this minor */
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struct vpe *get_vpe(int minor)
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{
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--- a/arch/mips/lantiq/prom.c
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+++ b/arch/mips/lantiq/prom.c
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@@ -31,10 +31,14 @@ EXPORT_SYMBOL_GPL(ebu_lock);
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*/
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static struct ltq_soc_info soc_info;
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+/* for Multithreading (APRP), vpe.c will use it */
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+unsigned long cp0_memsize;
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+
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const char *get_system_type(void)
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{
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return soc_info.sys_type;
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}
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+EXPORT_SYMBOL(ltq_soc_type);
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int ltq_soc_type(void)
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{
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--- a/arch/mips/include/asm/mipsmtregs.h
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+++ b/arch/mips/include/asm/mipsmtregs.h
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@@ -31,6 +31,9 @@
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#define read_c0_vpeconf1() __read_32bit_c0_register($1, 3)
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#define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val)
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+#define read_c0_vpeopt() __read_32bit_c0_register($1, 7)
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+#define write_c0_vpeopt(val) __write_32bit_c0_register($1, 7, val)
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+
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#define read_c0_tcstatus() __read_32bit_c0_register($2, 1)
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#define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val)
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@@ -376,6 +379,8 @@ do { \
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#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
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#define read_vpe_c0_vpeconf1() mftc0(1, 3)
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#define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val)
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+#define read_vpe_c0_vpeopt() mftc0(1, 7)
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+#define write_vpe_c0_vpeopt(val) mttc0(1, 7, val)
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#define read_vpe_c0_count() mftc0(9, 0)
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#define write_vpe_c0_count(val) mttc0(9, 0, val)
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#define read_vpe_c0_status() mftc0(12, 0)
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