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14940aee45
Removed upstreamed: target/linux/mvebu/patches-5.4/001-PCI-aardvark-Wait-for-endpoint-to-be-ready-before-tr.patch target/linux/mvebu/patches-5.4/016-PCI-aardvark-Train-link-immediately-after-enabling-t.patch target/linux/mvebu/patches-5.4/017-PCI-aardvark-Improve-link-training.patch target/linux/mvebu/patches-5.4/018-PCI-aardvark-Issue-PERST-via-GPIO.patch target/linux/mvebu/patches-5.4/020-arm64-dts-marvell-armada-37xx-Set-pcie_reset_pin-to-.patch The following patch does not apply to upstream any more and needs some more work to make it work fully again. I am not sure if we are still able to set the UART to a none standard baud rate. target/linux/ath79/patches-5.4/921-serial-core-add-support-for-boot-console-with-arbitr.patch These patches needed manually changes: target/linux/generic/pending-5.4/110-ehci_hcd_ignore_oc.patch target/linux/ipq806x/patches-5.4/0065-arm-override-compiler-flags.patch target/linux/layerscape/patches-5.4/804-crypto-0016-MLKU-114-1-crypto-caam-reduce-page-0-regs-access-to-.patch target/linux/mvebu/patches-5.4/019-PCI-aardvark-Add-PHY-support.patch target/linux/octeontx/patches-5.4/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch All others updated automatically. Compile-tested on: malta/le, armvirt/64, lantiq/xrx200 Runtime-tested on: malta/le, armvirt/64, lantiq/xrx200 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
27 lines
760 B
Diff
27 lines
760 B
Diff
From c4cd6fcae46fd14aed8665b7cf66d0954765a873 Mon Sep 17 00:00:00 2001
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From: Christian Lamparter <chunkeey@gmail.com>
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Date: Sat, 22 Aug 2020 18:19:21 +0200
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Subject: [PATCH] ARM: dts: BCM5301X: Specify pcie2 in the DT
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The SoC supports three pcie ports. Currently, only
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pcie0 and pcie1 are enabled. This patch adds the
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pcie2 port as well.
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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Reviewed-by: Scott Branden <scott.branden@broadcom.com>
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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--- a/arch/arm/boot/dts/bcm5301x.dtsi
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+++ b/arch/arm/boot/dts/bcm5301x.dtsi
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@@ -254,6 +254,10 @@
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reg = <0x00013000 0x1000>;
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};
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+ pcie2: pcie@14000 {
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+ reg = <0x00014000 0x1000>;
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+ };
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+
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usb2: usb2@21000 {
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reg = <0x00021000 0x1000>;
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