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9ac80a47ea
Tested on Luxul XWR-3150 (boot, NAND, PCIe, switch, Ethernet). Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
91 lines
1.8 KiB
Diff
91 lines
1.8 KiB
Diff
From 2addf9266a1d0f4ba59c9868b3effcd50de441a4 Mon Sep 17 00:00:00 2001
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From: Matthew Hagan <mnhagan88@gmail.com>
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Date: Fri, 6 Aug 2021 21:44:33 +0100
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Subject: [PATCH] ARM: dts: NSP: Add Ax stepping modifications
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While uncommon, some Ax NSP SoCs exist in the wild. This stepping
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requires a modified secondary CPU boot-reg and removal of DMA coherency
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properties. Without these modifications, the secondary CPU will be
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inactive and many peripherals will exhibit undefined behaviour.
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Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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arch/arm/boot/dts/bcm-nsp-ax.dtsi | 70 +++++++++++++++++++++++++++++++
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1 file changed, 70 insertions(+)
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create mode 100644 arch/arm/boot/dts/bcm-nsp-ax.dtsi
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--- /dev/null
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+++ b/arch/arm/boot/dts/bcm-nsp-ax.dtsi
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@@ -0,0 +1,70 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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+/*
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+ * Broadcom Northstar Plus Ax stepping-specific bindings.
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+ * Notable differences from B0+ are the secondary-boot-reg and
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+ * lack of DMA coherency.
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+ */
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+
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+&cpu1 {
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+ secondary-boot-reg = <0xffff042c>;
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+};
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+
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+&dma {
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+ /delete-property/ dma-coherent;
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+};
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+
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+&sdio {
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+ /delete-property/ dma-coherent;
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+};
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+
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+&amac0 {
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+ /delete-property/ dma-coherent;
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+};
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+
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+&amac1 {
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+ /delete-property/ dma-coherent;
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+};
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+
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+&amac2 {
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+ /delete-property/ dma-coherent;
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+};
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+
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+&ehci0 {
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+ /delete-property/ dma-coherent;
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+};
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+
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+&mailbox {
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+ /delete-property/ dma-coherent;
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+};
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+
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+&xhci {
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+ /delete-property/ dma-coherent;
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+};
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+
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+&ehci0 {
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+ /delete-property/ dma-coherent;
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+};
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+
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+&ohci0 {
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+ /delete-property/ dma-coherent;
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+};
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+
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+&i2c0 {
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+ /delete-property/ dma-coherent;
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+};
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+
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+&sata {
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+ /delete-property/ dma-coherent;
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+};
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+
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+&pcie0 {
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+ /delete-property/ dma-coherent;
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+};
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+
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+&pcie1 {
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+ /delete-property/ dma-coherent;
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+};
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+
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+&pcie2 {
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+ /delete-property/ dma-coherent;
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+};
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