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ae5cb164cd
Commit 4c8dd973ef ("ath9k: OF: qca,disable-(2|5)ghz => ieee80211-freq-limit")
removed "qca,disable-5ghz" and "qca,disable-2ghz". Switch to upstream
ieee80211-freq-limit.
Signed-off-by: Nick Hainke <vincent@systemli.org>
126 lines
2.2 KiB
Plaintext
126 lines
2.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "ar9344.dtsi"
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#include "ar934x_senao_loader.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "araknis,an-300-ap-i-n", "qca,ar9344";
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model = "Araknis AN-300-AP-I-N";
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aliases {
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label-mac-device = ð0;
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led-boot = &led_power;
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led-failsafe = &led_power;
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led-upgrade = &led_power;
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};
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keys {
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compatible = "gpio-keys";
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reset {
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linux,code = <KEY_RESTART>;
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gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_power: power {
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label = "amber:power";
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gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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wifi5g {
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label = "blue:wifi5g";
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gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy0tpt";
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};
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wps {
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label = "blue:wps";
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gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
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};
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};
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ath9k-leds {
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compatible = "gpio-leds";
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wifi2g {
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label = "blue:wifi2g";
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gpios = <&ath9k 0 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy1tpt";
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};
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};
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};
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&mdio0 {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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eee-broken-100tx;
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eee-broken-1000t;
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};
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};
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ð0 {
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status = "okay";
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nvmem-cells = <&macaddr_art_0>;
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nvmem-cell-names = "mac-address";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-txid";
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pll-data = <0x02000000 0x00000101 0x00001313>;
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};
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&pcie {
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status = "okay";
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ath9k: wifi@0,0,0 {
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compatible = "pci168c,0030";
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reg = <0x0 0 0 0 0>;
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nvmem-cells = <&macaddr_art_0>, <&calibration_art_5000>;
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nvmem-cell-names = "mac-address", "calibration";
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mac-address-increment = <1>;
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ieee80211-freq-limit = <2402000 2482000>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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};
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&wmac {
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status = "okay";
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ieee80211-freq-limit = <4900000 5990000>;
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nvmem-cells = <&macaddr_art_0>, <&calibration_art_1000>;
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nvmem-cell-names = "mac-address", "calibration";
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mac-address-increment = <2>;
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};
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&art {
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_art_0: macaddr@0 {
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reg = <0x0 0x6>;
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};
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calibration_art_1000: calibration@1000 {
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reg = <0x1000 0x440>;
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};
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calibration_art_5000: calibration@5000 {
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reg = <0x5000 0x440>;
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};
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};
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