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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
78 lines
2.5 KiB
Diff
78 lines
2.5 KiB
Diff
From d57245d420a2ced6a588cc6e03e2eaacbbf1bfb2 Mon Sep 17 00:00:00 2001
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From: Minda Chen <minda.chen@starfivetech.com>
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Date: Thu, 18 May 2023 19:27:45 +0800
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Subject: [PATCH 088/122] dt-bindings: phy: Add StarFive JH7110 PCIe PHY
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Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding.
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PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY.
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Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
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Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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---
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.../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++++++++++++++++
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1 file changed, 58 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
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@@ -0,0 +1,58 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive JH7110 PCIe 2.0 PHY
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+
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+maintainers:
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+ - Minda Chen <minda.chen@starfivetech.com>
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+
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+properties:
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+ compatible:
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+ const: starfive,jh7110-pcie-phy
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+
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+ reg:
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+ maxItems: 1
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+
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+ "#phy-cells":
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+ const: 0
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+
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+ starfive,sys-syscon:
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+ $ref: /schemas/types.yaml#/definitions/phandle-array
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+ items:
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+ - items:
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+ - description: phandle to System Register Controller sys_syscon node.
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+ - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY.
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+ description:
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+ The phandle to System Register Controller syscon node and the PHY connect offset
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+ of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller.
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+
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+ starfive,stg-syscon:
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+ $ref: /schemas/types.yaml#/definitions/phandle-array
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+ items:
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+ - items:
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+ - description: phandle to System Register Controller stg_syscon node.
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+ - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register.
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+ - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register.
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+ description:
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+ The phandle to System Register Controller syscon node and the offset
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+ of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset.
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+
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+required:
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+ - compatible
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+ - reg
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+ - "#phy-cells"
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ phy@10210000 {
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+ compatible = "starfive,jh7110-pcie-phy";
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+ reg = <0x10210000 0x10000>;
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+ #phy-cells = <0>;
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+ starfive,sys-syscon = <&sys_syscon 0x18>;
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+ starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
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+ };
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