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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
291 lines
7.0 KiB
Diff
291 lines
7.0 KiB
Diff
From 76bc84c399f11c7d6a37fe68cbd5f182e4c18369 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Sat, 1 Apr 2023 19:19:33 +0800
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Subject: [PATCH 023/122] riscv: dts: starfive: Add StarFive JH7110 VisionFive
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2 board device tree
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Add a minimal device tree for StarFive JH7110 VisionFive 2 board
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which has version A and version B. Support booting and basic
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clock/reset/pinctrl/uart drivers.
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Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
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Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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Acked-by: Conor Dooley <conor.dooley@microchip.com>
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
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Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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---
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arch/riscv/boot/dts/starfive/Makefile | 6 +-
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.../jh7110-starfive-visionfive-2-v1.2a.dts | 13 ++
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.../jh7110-starfive-visionfive-2-v1.3b.dts | 13 ++
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.../jh7110-starfive-visionfive-2.dtsi | 215 ++++++++++++++++++
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4 files changed, 246 insertions(+), 1 deletion(-)
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create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
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create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
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create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
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--- a/arch/riscv/boot/dts/starfive/Makefile
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+++ b/arch/riscv/boot/dts/starfive/Makefile
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@@ -1,2 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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-dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
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+dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb
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+dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
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+
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+dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
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+dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
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--- /dev/null
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+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
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@@ -0,0 +1,13 @@
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+// SPDX-License-Identifier: GPL-2.0 OR MIT
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+/*
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+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
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+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
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+ */
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+
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+/dts-v1/;
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+#include "jh7110-starfive-visionfive-2.dtsi"
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+
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+/ {
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+ model = "StarFive VisionFive 2 v1.2A";
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+ compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
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+};
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--- /dev/null
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+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
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@@ -0,0 +1,13 @@
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+// SPDX-License-Identifier: GPL-2.0 OR MIT
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+/*
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+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
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+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
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+ */
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+
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+/dts-v1/;
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+#include "jh7110-starfive-visionfive-2.dtsi"
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+
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+/ {
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+ model = "StarFive VisionFive 2 v1.3B";
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+ compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
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+};
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--- /dev/null
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+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
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@@ -0,0 +1,215 @@
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+// SPDX-License-Identifier: GPL-2.0 OR MIT
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+/*
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+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
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+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
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+ */
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+
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+/dts-v1/;
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+#include "jh7110.dtsi"
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+#include "jh7110-pinfunc.h"
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+#include <dt-bindings/gpio/gpio.h>
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+
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+/ {
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+ aliases {
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+ i2c0 = &i2c0;
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+ i2c2 = &i2c2;
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+ i2c5 = &i2c5;
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+ i2c6 = &i2c6;
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+ serial0 = &uart0;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ cpus {
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+ timebase-frequency = <4000000>;
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+ };
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+
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+ memory@40000000 {
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+ device_type = "memory";
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+ reg = <0x0 0x40000000 0x1 0x0>;
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+ };
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+
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+ gpio-restart {
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+ compatible = "gpio-restart";
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+ gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
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+ priority = <224>;
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+ };
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+};
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+
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+&gmac0_rgmii_rxin {
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+ clock-frequency = <125000000>;
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+};
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+
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+&gmac0_rmii_refin {
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+ clock-frequency = <50000000>;
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+};
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+
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+&gmac1_rgmii_rxin {
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+ clock-frequency = <125000000>;
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+};
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+
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+&gmac1_rmii_refin {
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+ clock-frequency = <50000000>;
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+};
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+
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+&i2srx_bclk_ext {
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+ clock-frequency = <12288000>;
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+};
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+
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+&i2srx_lrck_ext {
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+ clock-frequency = <192000>;
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+};
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+
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+&i2stx_bclk_ext {
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+ clock-frequency = <12288000>;
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+};
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+
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+&i2stx_lrck_ext {
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+ clock-frequency = <192000>;
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+};
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+
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+&mclk_ext {
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+ clock-frequency = <12288000>;
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+};
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+
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+&osc {
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+ clock-frequency = <24000000>;
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+};
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+
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+&rtc_osc {
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+ clock-frequency = <32768>;
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+};
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+
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+&tdm_ext {
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+ clock-frequency = <49152000>;
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+};
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+
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+&i2c0 {
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+ clock-frequency = <100000>;
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+ i2c-sda-hold-time-ns = <300>;
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+ i2c-sda-falling-time-ns = <510>;
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+ i2c-scl-falling-time-ns = <510>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c0_pins>;
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+ status = "okay";
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+};
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+
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+&i2c2 {
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+ clock-frequency = <100000>;
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+ i2c-sda-hold-time-ns = <300>;
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+ i2c-sda-falling-time-ns = <510>;
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+ i2c-scl-falling-time-ns = <510>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c2_pins>;
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+ status = "okay";
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+};
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+
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+&i2c5 {
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+ clock-frequency = <100000>;
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+ i2c-sda-hold-time-ns = <300>;
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+ i2c-sda-falling-time-ns = <510>;
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+ i2c-scl-falling-time-ns = <510>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c5_pins>;
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+ status = "okay";
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+};
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+
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+&i2c6 {
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+ clock-frequency = <100000>;
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+ i2c-sda-hold-time-ns = <300>;
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+ i2c-sda-falling-time-ns = <510>;
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+ i2c-scl-falling-time-ns = <510>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c6_pins>;
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+ status = "okay";
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+};
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+
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+&sysgpio {
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+ i2c0_pins: i2c0-0 {
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+ i2c-pins {
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+ pinmux = <GPIOMUX(57, GPOUT_LOW,
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+ GPOEN_SYS_I2C0_CLK,
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+ GPI_SYS_I2C0_CLK)>,
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+ <GPIOMUX(58, GPOUT_LOW,
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+ GPOEN_SYS_I2C0_DATA,
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+ GPI_SYS_I2C0_DATA)>;
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+ bias-disable; /* external pull-up */
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+ input-enable;
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+ input-schmitt-enable;
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+ };
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+ };
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+
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+ i2c2_pins: i2c2-0 {
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+ i2c-pins {
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+ pinmux = <GPIOMUX(3, GPOUT_LOW,
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+ GPOEN_SYS_I2C2_CLK,
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+ GPI_SYS_I2C2_CLK)>,
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+ <GPIOMUX(2, GPOUT_LOW,
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+ GPOEN_SYS_I2C2_DATA,
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+ GPI_SYS_I2C2_DATA)>;
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+ bias-disable; /* external pull-up */
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+ input-enable;
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+ input-schmitt-enable;
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+ };
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+ };
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+
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+ i2c5_pins: i2c5-0 {
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+ i2c-pins {
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+ pinmux = <GPIOMUX(19, GPOUT_LOW,
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+ GPOEN_SYS_I2C5_CLK,
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+ GPI_SYS_I2C5_CLK)>,
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+ <GPIOMUX(20, GPOUT_LOW,
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+ GPOEN_SYS_I2C5_DATA,
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+ GPI_SYS_I2C5_DATA)>;
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+ bias-disable; /* external pull-up */
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+ input-enable;
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+ input-schmitt-enable;
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+ };
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+ };
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+
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+ i2c6_pins: i2c6-0 {
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+ i2c-pins {
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+ pinmux = <GPIOMUX(16, GPOUT_LOW,
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+ GPOEN_SYS_I2C6_CLK,
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+ GPI_SYS_I2C6_CLK)>,
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+ <GPIOMUX(17, GPOUT_LOW,
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+ GPOEN_SYS_I2C6_DATA,
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+ GPI_SYS_I2C6_DATA)>;
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+ bias-disable; /* external pull-up */
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+ input-enable;
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+ input-schmitt-enable;
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+ };
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+ };
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+
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+ uart0_pins: uart0-0 {
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+ tx-pins {
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+ pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
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+ GPOEN_ENABLE,
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+ GPI_NONE)>;
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+ bias-disable;
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+ drive-strength = <12>;
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+ input-disable;
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+ input-schmitt-disable;
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+ slew-rate = <0>;
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+ };
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+
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+ rx-pins {
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+ pinmux = <GPIOMUX(6, GPOUT_LOW,
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+ GPOEN_DISABLE,
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+ GPI_SYS_UART0_RX)>;
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+ bias-disable; /* external pull-up */
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+ drive-strength = <2>;
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+ input-enable;
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+ input-schmitt-enable;
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+ slew-rate = <0>;
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+ };
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+ };
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+};
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+
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+&uart0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart0_pins>;
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+ status = "okay";
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+};
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