mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-28 09:39:00 +00:00
176 lines
4.2 KiB
Diff
176 lines
4.2 KiB
Diff
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -20,7 +20,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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- cpu@0 {
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+ cpu0: cpu@0 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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@@ -30,7 +30,7 @@
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qcom,saw = <&saw0>;
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};
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- cpu@1 {
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+ cpu1: cpu@1 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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@@ -67,7 +67,7 @@
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no-map;
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};
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- smem@41000000 {
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+ smem: smem@41000000 {
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reg = <0x41000000 0x200000>;
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no-map;
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};
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@@ -128,6 +128,7 @@
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gpio-ranges = <&qcom_pinmux 0 0 69>;
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#gpio-cells = <2>;
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interrupt-controller;
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+ #address-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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@@ -155,6 +156,7 @@
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function = "pcie3_rst";
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drive-strength = <12>;
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bias-disable;
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+ output-low;
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};
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};
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@@ -190,6 +192,7 @@
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intc: interrupt-controller@2000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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+ #address-cells = <0>;
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#interrupt-cells = <3>;
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reg = <0x02000000 0x1000>,
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<0x02002000 0x1000>;
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@@ -219,21 +222,23 @@
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acc0: clock-controller@2088000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
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+ clock-output-names = "acpu0_aux";
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};
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acc1: clock-controller@2098000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
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+ clock-output-names = "acpu1_aux";
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};
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saw0: regulator@2089000 {
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- compatible = "qcom,saw2";
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+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
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reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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saw1: regulator@2099000 {
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- compatible = "qcom,saw2";
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+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
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reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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@@ -251,7 +256,7 @@
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syscon-tcsr = <&tcsr>;
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- serial@12490000 {
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+ gsbi2_serial: serial@12490000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x12490000 0x1000>,
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<0x12480000 0x1000>;
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@@ -326,7 +331,7 @@
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syscon-tcsr = <&tcsr>;
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- serial@1a240000 {
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+ gsbi5_serial: serial@1a240000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x1a240000 0x1000>,
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<0x1a200000 0x1000>;
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@@ -397,7 +402,7 @@
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status = "disabled";
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};
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- sata@29000000 {
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+ sata: sata@29000000 {
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compatible = "qcom,ipq806x-ahci", "generic-ahci";
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reg = <0x29000000 0x180>;
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@@ -430,13 +435,35 @@
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reg = <0x00700000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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+
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+ tsens_calib: calib@400 {
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+ reg = <0x400 0xb>;
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+ };
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+ tsens_backup: backup@410 {
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+ reg = <0x410 0xb>;
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+ };
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+ speedbin_efuse: speedbin@0c0 {
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+ reg = <0x0c0 0x4>;
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+ };
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};
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gcc: clock-controller@900000 {
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- compatible = "qcom,gcc-ipq8064";
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+ compatible = "qcom,gcc-ipq8064", "syscon";
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reg = <0x00900000 0x4000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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+ #power-domain-cells = <1>;
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+
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+ tsens: thermal-sensor@900000 {
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+ compatible = "qcom,ipq8064-tsens";
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+
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+ nvmem-cells = <&tsens_calib>, <&tsens_backup>;
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+ nvmem-cell-names = "calib", "calib_backup";
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+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "uplow";
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+ #thermal-sensor-cells = <1>;
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+ #qcom,sensors = <11>;
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+ };
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};
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tcsr: syscon@1a400000 {
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@@ -740,13 +767,13 @@
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qcom,ee = <0>;
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};
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- amba {
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- compatible = "simple-bus";
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+ amba: amba {
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+ compatible = "arm,amba-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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- sdcc@12400000 {
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+ sdcc1: sdcc@12400000 {
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status = "disabled";
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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@@ -760,13 +787,12 @@
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non-removable;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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- mmc-ddr-1_8v;
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vmmc-supply = <&vsdcc_fixed>;
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dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
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dma-names = "tx", "rx";
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};
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- sdcc@12180000 {
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+ sdcc3: sdcc@12180000 {
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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status = "disabled";
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