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e9d92bf1e1
Refreshed all patches. Removed upstreamed: - 203-MIPS-ath79-fix-restart.patch - 0013-MIPS-ath79-fix-system-restart.patch - 180-earlycon-initialize-port-uartclk-based-on-clock-frequency-property.patch - 181-earlycon-remove-hardcoded-port-uartclk-initialization-in-of_setup_earlycon. patch - 700-1-6-e1000e-Remove-Other-from-EIAC.patch - 700-2-6-Partial-revert-e1000e-Avoid-receiver-overrun-interrupt-bursts.patch - 700-3-6-e1000e-Fix-queue-interrupt-re-raising-in-Other-interrupt.patch - 700-4-6-e1000e-Avoid-missed-interrupts-following-ICR-read.patch Compile-tested on: cns3xxx, imx6 Runtime-tested on: cns3xxx, imx6 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
184 lines
5.9 KiB
Diff
184 lines
5.9 KiB
Diff
From 2034addc7e193dc81d7ca60d8884832751b76758 Mon Sep 17 00:00:00 2001
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From: Ajay Kishore <akisho@codeaurora.org>
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Date: Tue, 24 Jan 2017 14:14:16 +0530
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Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps
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For IPQ806x targets, TZ protects the registers that are used to
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configure the routing of interrupts to a target processor.
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To resolve this, this patch uses scm call to route GPIO interrupts
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to application processor. Also the scm call interface is changed.
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Change-Id: Ib6c06829d04bc8c20483c36e63da92e26cdef9ce
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Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
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---
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drivers/firmware/qcom_scm-32.c | 17 +++++++++++++++++
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drivers/firmware/qcom_scm-64.c | 9 +++++++++
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drivers/firmware/qcom_scm.c | 13 +++++++++++++
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drivers/firmware/qcom_scm.h | 8 ++++++++
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drivers/pinctrl/qcom/pinctrl-msm.c | 34 ++++++++++++++++++++++++++++------
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include/linux/qcom_scm.h | 3 ++-
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6 files changed, 77 insertions(+), 7 deletions(-)
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--- a/drivers/firmware/qcom_scm-32.c
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+++ b/drivers/firmware/qcom_scm-32.c
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@@ -561,6 +561,24 @@ int __qcom_scm_pas_mss_reset(struct devi
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return ret ? : le32_to_cpu(out);
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}
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+int __qcom_scm_pinmux_read(u32 svc_id, u32 cmd_id, u32 arg1)
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+{
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+ s32 ret;
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+
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+ ret = qcom_scm_call_atomic1(svc_id, cmd_id, arg1);
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+
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+ return ret;
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+}
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+
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+int __qcom_scm_pinmux_write(u32 svc_id, u32 cmd_id, u32 arg1, u32 arg2)
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+{
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+ s32 ret;
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+
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+ ret = qcom_scm_call_atomic2(svc_id, cmd_id, arg1, arg2);
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+
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+ return ret;
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+}
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+
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int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
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{
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struct {
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--- a/drivers/firmware/qcom_scm-64.c
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+++ b/drivers/firmware/qcom_scm-64.c
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@@ -366,6 +366,16 @@ int __qcom_scm_pas_mss_reset(struct devi
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return ret ? : res.a1;
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}
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+int __qcom_scm_pinmux_read(u32 svc_id, u32 cmd_id, u32 arg1)
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+{
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+ return -ENOTSUPP;
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+}
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+
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+int __qcom_scm_pinmux_write(u32 svc_id, u32 cmd_id, u32 arg1, u32 arg2)
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+{
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+ return -ENOTSUPP;
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+}
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+
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int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
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{
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struct qcom_scm_desc desc = {0};
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--- a/drivers/firmware/qcom_scm.c
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+++ b/drivers/firmware/qcom_scm.c
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@@ -470,3 +470,16 @@ static int __init qcom_scm_init(void)
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return platform_driver_register(&qcom_scm_driver);
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}
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subsys_initcall(qcom_scm_init);
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+
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+int qcom_scm_pinmux_read(u32 arg1)
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+{
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+ return __qcom_scm_pinmux_read(SCM_SVC_IO_ACCESS, SCM_IO_READ, arg1);
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+}
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+EXPORT_SYMBOL(qcom_scm_pinmux_read);
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+
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+int qcom_scm_pinmux_write(u32 arg1, u32 arg2)
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+{
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+ return __qcom_scm_pinmux_write(SCM_SVC_IO_ACCESS, SCM_IO_WRITE,
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+ arg1, arg2);
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+}
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+EXPORT_SYMBOL(qcom_scm_pinmux_write);
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--- a/drivers/firmware/qcom_scm.h
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+++ b/drivers/firmware/qcom_scm.h
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@@ -58,6 +58,13 @@ extern int __qcom_scm_pas_auth_and_rese
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extern int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral);
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extern int __qcom_scm_pas_mss_reset(struct device *dev, bool reset);
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+#define SCM_IO_READ 1
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+#define SCM_IO_WRITE 2
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+#define SCM_SVC_IO_ACCESS 0x5
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+
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+s32 __qcom_scm_pinmux_read(u32 svc_id, u32 cmd_id, u32 arg1);
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+s32 __qcom_scm_pinmux_write(u32 svc_id, u32 cmd_id, u32 arg1, u32 arg2);
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+
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/* common error codes */
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#define QCOM_SCM_V2_EBUSY -12
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#define QCOM_SCM_ENOMEM -5
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--- a/drivers/pinctrl/qcom/pinctrl-msm.c
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+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
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@@ -30,7 +30,8 @@
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#include <linux/reboot.h>
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#include <linux/pm.h>
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#include <linux/log2.h>
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-
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+#include <linux/qcom_scm.h>
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+#include <linux/io.h>
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#include "../core.h"
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#include "../pinconf.h"
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#include "pinctrl-msm.h"
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@@ -646,6 +647,9 @@ static void msm_gpio_irq_ack(struct irq_
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const struct msm_pingroup *g;
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unsigned long flags;
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u32 val;
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+ u32 addr;
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+ int ret;
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+ const __be32 *reg;
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g = &pctrl->soc->groups[d->hwirq];
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@@ -684,11 +688,30 @@ static int msm_gpio_irq_set_type(struct
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else
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clear_bit(d->hwirq, pctrl->dual_edge_irqs);
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+ int ret = of_device_is_compatible(pctrl->dev->of_node,
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+ "qcom,ipq8064-pinctrl");
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/* Route interrupts to application cpu */
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- val = readl(pctrl->regs + g->intr_target_reg);
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- val &= ~(7 << g->intr_target_bit);
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- val |= g->intr_target_kpss_val << g->intr_target_bit;
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- writel(val, pctrl->regs + g->intr_target_reg);
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+ if (!ret) {
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+ val = readl(pctrl->regs + g->intr_target_reg);
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+ val &= ~(7 << g->intr_target_bit);
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+ val |= g->intr_target_kpss_val << g->intr_target_bit;
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+ writel(val, pctrl->regs + g->intr_target_reg);
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+ } else {
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+ const __be32 *reg = of_get_property(pctrl->dev->of_node, "reg", NULL);
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+ if (reg) {
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+ u32 addr = be32_to_cpup(reg) + g->intr_target_reg;
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+ val = qcom_scm_pinmux_read(addr);
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+ __iormb();
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+
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+ val &= ~(7 << g->intr_target_bit);
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+ val |= g->intr_target_kpss_val << g->intr_target_bit;
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+
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+ __iowmb();
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+ ret = qcom_scm_pinmux_write(addr, val);
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+ if (ret)
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+ pr_err("\n Routing interrupts to Apps proc failed");
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+ }
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+ }
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/* Update configuration for gpio.
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* RAW_STATUS_EN is left on for all gpio irqs. Due to the
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@@ -962,4 +985,3 @@ int msm_pinctrl_remove(struct platform_d
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return 0;
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}
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EXPORT_SYMBOL(msm_pinctrl_remove);
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-
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--- a/include/linux/qcom_scm.h
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+++ b/include/linux/qcom_scm.h
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@@ -43,6 +43,8 @@ extern int qcom_scm_set_remote_state(u32
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extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
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extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
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extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
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+extern s32 qcom_scm_pinmux_read(u32 arg1);
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+extern s32 qcom_scm_pinmux_write(u32 arg1, u32 arg2);
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#else
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static inline
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int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
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@@ -73,5 +75,7 @@ qcom_scm_set_remote_state(u32 state,u32
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static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
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static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
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static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
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+extern s32 qcom_scm_pinmux_read(u32 arg1) { return -ENODEV; }
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+extern s32 qcom_scm_pinmux_write(u32 arg1, u32 arg2) { return -ENODEV; }
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#endif
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#endif
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