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88bf652525
Reorganize dtsi patches with upstream version and drop dtsi in 5.15 files. Also add an additional upstream patch for hwspinlock support. Refresh all the dts with needed changes. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
189 lines
3.6 KiB
Diff
189 lines
3.6 KiB
Diff
From 504188183408fac0f61b59f5ed8ea1773fe43669 Mon Sep 17 00:00:00 2001
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From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
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Date: Wed, 15 Jun 2022 16:59:30 +0200
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Subject: [PATCH 2/2] ARM: dts: qcom: add MDIO dedicated controller node for
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ipq806x
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Add MDIO dedicated controller attached to gmac0 and fix rb3011 dts to
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correctly use the new tag.
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Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
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---
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arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 134 +++++++++++-----------
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 14 +++
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2 files changed, 81 insertions(+), 67 deletions(-)
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--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
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@@ -24,73 +24,6 @@
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device_type = "memory";
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};
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- mdio0: mdio-0 {
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- status = "okay";
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- compatible = "virtual,mdio-gpio";
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- gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
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- <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
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- #address-cells = <1>;
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- #size-cells = <0>;
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-
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- pinctrl-0 = <&mdio0_pins>;
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- pinctrl-names = "default";
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-
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- switch0: switch@10 {
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- compatible = "qca,qca8337";
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- #address-cells = <1>;
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- #size-cells = <0>;
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-
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- dsa,member = <0 0>;
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-
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- pinctrl-0 = <&sw0_reset_pin>;
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- pinctrl-names = "default";
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-
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- reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
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- reg = <0x10>;
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-
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- ports {
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- #address-cells = <1>;
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- #size-cells = <0>;
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-
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- switch0cpu: port@0 {
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- reg = <0>;
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- label = "cpu";
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- ethernet = <&gmac0>;
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- phy-mode = "rgmii-id";
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- fixed-link {
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- speed = <1000>;
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- full-duplex;
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- };
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- };
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-
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- port@1 {
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- reg = <1>;
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- label = "sw1";
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- };
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-
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- port@2 {
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- reg = <2>;
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- label = "sw2";
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- };
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-
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- port@3 {
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- reg = <3>;
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- label = "sw3";
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- };
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-
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- port@4 {
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- reg = <4>;
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- label = "sw4";
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- };
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-
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- port@5 {
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- reg = <5>;
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- label = "sw5";
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- };
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- };
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- };
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- };
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-
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mdio1: mdio-1 {
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status = "okay";
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compatible = "virtual,mdio-gpio";
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@@ -220,6 +153,73 @@
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status = "okay";
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};
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+&mdio0 {
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+ status = "okay";
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+ compatible = "virtual,mdio-gpio";
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+ gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
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+ <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ pinctrl-0 = <&mdio0_pins>;
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+ pinctrl-names = "default";
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+
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+ switch0: switch@10 {
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+ compatible = "qca,qca8337";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ dsa,member = <0 0>;
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+
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+ pinctrl-0 = <&sw0_reset_pin>;
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+ pinctrl-names = "default";
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+
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+ reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
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+ reg = <0x10>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ switch0cpu: port@0 {
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+ reg = <0>;
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+ label = "cpu";
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+ ethernet = <&gmac0>;
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+ phy-mode = "rgmii-id";
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ label = "sw1";
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ label = "sw2";
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+ label = "sw3";
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+ };
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+
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+ port@4 {
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+ reg = <4>;
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+ label = "sw4";
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+ };
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+
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+ port@5 {
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+ reg = <5>;
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+ label = "sw5";
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+ };
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+ };
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+ };
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+};
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+
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&gmac0 {
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status = "okay";
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -1446,6 +1446,20 @@
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};
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};
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+ mdio0: mdio@37000000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ compatible = "qcom,ipq8064-mdio", "syscon";
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+ reg = <0x37000000 0x200000>;
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+ resets = <&gcc GMAC_CORE1_RESET>;
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+ reset-names = "stmmaceth";
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+ clocks = <&gcc GMAC_CORE1_CLK>;
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+ clock-names = "stmmaceth";
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+
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+ status = "disabled";
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+ };
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+
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vsdcc_fixed: vsdcc-regulator {
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compatible = "regulator-fixed";
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regulator-name = "SDCC Power";
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