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c6ddf8d502
Many changes were done in drivers/pinctrl/bcm/pinctrl-bcm2835.c between
5.4.171 and 5.4.179.
The following 3 patches do not apply any more:
* target/linux/bcm27xx/patches-5.4/950-0316-pinctrl-bcm2835-Add-support-for-BCM2711-pull-up-func.patch
This was already integrated in kernel v5.4-rc1, it was never needed.
* target/linux/bcm27xx/patches-5.4/950-0328-Revert-pinctrl-bcm2835-Pass-irqchip-when-adding-gpio.patch
* target/linux/bcm27xx/patches-5.4/950-0362-pinctrl-bcm2835-Change-init-order-for-gpio-hogs.patch
I think these were done to fix the problem which was really fixed in
commit 75278f1aff5e ("pinctrl: bcm2835: Change init order for gpio
hogs") from v5.4.175
target/linux/generic/backport-5.4/716-v5.5-net-sfp-move-fwnode-parsing-into-sfp-bus-layer.patch
Move fwnode_device_is_available to the same position as in kernel 5.10.
target/linux/layerscape/patches-5.4/302-dts-0083-arm64-ls1028a-qds-correct-bus-of-rtc.patch
Applied in commit 65816c1034769e714edb70f59a33bc5472d9e55f ("arm64: dts:
ls1028a-qds: move rtc node to the correct i2c bus")
Compile-tested: lantiq/xrx200, bcm27xx/bcm2710
Run-tested: lantiq/xrx200
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
54 lines
1.8 KiB
Diff
54 lines
1.8 KiB
Diff
From cfe0832e8306cd9955f682b7314a5a6fc3b9d514 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Thu, 2 May 2019 15:11:05 -0700
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Subject: [PATCH] clk: bcm2835: Add support for setting leaf clock
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rates while running.
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As long as you wait for !BUSY, you can do glitch-free updates of clock
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rate while the clock is running.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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---
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drivers/clk/bcm/clk-bcm2835.c | 22 +++++++++++++---------
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1 file changed, 13 insertions(+), 9 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -1109,15 +1109,19 @@ static int bcm2835_clock_set_rate(struct
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spin_lock(&cprman->regs_lock);
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- /*
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- * Setting up frac support
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- *
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- * In principle it is recommended to stop/start the clock first,
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- * but as we set CLK_SET_RATE_GATE during registration of the
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- * clock this requirement should be take care of by the
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- * clk-framework.
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+ ctl = cprman_read(cprman, data->ctl_reg);
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+
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+ /* If the clock is running, we have to pause clock generation while
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+ * updating the control and div regs. This is glitchless (no clock
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+ * signals generated faster than the rate) but each reg access is two
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+ * OSC cycles so the clock will slow down for a moment.
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*/
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- ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
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+ if (ctl & CM_ENABLE) {
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+ cprman_write(cprman, data->ctl_reg, ctl & ~CM_ENABLE);
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+ bcm2835_clock_wait_busy(clock);
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+ }
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+
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+ ctl &= ~CM_FRAC;
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ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
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cprman_write(cprman, data->ctl_reg, ctl);
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@@ -1489,7 +1493,7 @@ static struct clk_hw *bcm2835_register_c
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init.ops = &bcm2835_vpu_clock_clk_ops;
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} else {
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init.ops = &bcm2835_clock_clk_ops;
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- init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
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+ init.flags |= CLK_SET_PARENT_GATE;
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/* If the clock wasn't actually enabled at boot, it's not
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* critical.
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