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ee3067c588
Bump kernel to 4.4.44. Compile-tested on ar71xx, ramips/mt7621 and x86/64.
.44 has been run-tested on the 17.01 branch here on ar71xx and mt7621.
Signed-off-by: Stijn Segers <francesco.borromini@inventati.org>
(cherry picked from commit 20996edd68)
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Conflicts:
target/linux/ar71xx/patches-4.4/920-usb-chipidea-AR933x-platform-support.patch
target/linux/ar71xx/patches-4.4/930-chipidea-pullup.patch
57 lines
1.9 KiB
Diff
57 lines
1.9 KiB
Diff
From a58c6360b9eb3a2374b0b069ba9ce7baec0f26df Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
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Date: Thu, 24 Mar 2016 14:24:22 +0100
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Subject: [PATCH 3/3] serial: imx: make sure unhandled irqs are disabled
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Make sure that events that are not handled in the irq function don't
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trigger an interrupt.
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When the serial port is operated in DTE mode, the events for DCD and RI
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events are enabled after a system reset by default.
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Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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Signed-off-by: Petr Štetiar <ynezz@true.cz>
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---
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drivers/tty/serial/imx.c | 23 ++++++++++++++++++++++-
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1 file changed, 22 insertions(+), 1 deletion(-)
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--- a/drivers/tty/serial/imx.c
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+++ b/drivers/tty/serial/imx.c
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@@ -1184,11 +1184,32 @@ static int imx_startup(struct uart_port
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temp |= (UCR2_RXEN | UCR2_TXEN);
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if (!sport->have_rtscts)
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temp |= UCR2_IRTS;
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+ /*
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+ * make sure the edge sensitive RTS-irq is disabled,
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+ * we're using RTSD instead.
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+ */
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+ if (!is_imx1_uart(sport))
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+ temp &= ~UCR2_RTSEN;
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writel(temp, sport->port.membase + UCR2);
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if (!is_imx1_uart(sport)) {
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temp = readl(sport->port.membase + UCR3);
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- temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
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+
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+ /*
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+ * The effect of RI and DCD differs depending on the UFCR_DCEDTE
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+ * bit. In DCE mode they control the outputs, in DTE mode they
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+ * enable the respective irqs. At least the DCD irq cannot be
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+ * cleared on i.MX25 at least, so it's not usable and must be
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+ * disabled. I don't have test hardware to check if RI has the
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+ * same problem but I consider this likely so it's disabled for
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+ * now, too.
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+ */
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+ temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP |
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+ UCR3_RI | UCR3_DCD;
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+
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+ if (sport->dte_mode)
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+ temp &= ~(UCR3_RI | UCR3_DCD);
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+
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writel(temp, sport->port.membase + UCR3);
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}
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