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df8e6be59a
This adds support for the RTL838x Architecture. SoCs of this type are used in managed and un-managed Switches and Routers with 8-28 ports. Drivers are provided for SoC initialization, GPIOs, Flash, Ethernet including a DSA switch driver and internal and external PHYs used with these switches. Supported SoCs: RTL8380M RTL8381M RTL8382M The kernel will also boot on the following RTL839x SoCs, however driver support apart from spi-nor is missing: RTL8390 RTL8391 RTL8393 The following PHYs are supported: RTL8214FC (Quad QSGMII multiplexing GMAC and SFP port) RTL8218B internal: internal PHY of the RTL838x chips RTL8318b external (QSGMII 8-port GMAC phy) RTL8382M SerDes for 2 SFP ports Initialization sequences for the PHYs are provided in the form of firmware files. Flash driver supports 3 / 4 byte access DSA switch driver supports VLANs, port isolation, STP and port mirroring. The ALLNET ALL-SG8208M is supported as Proof of Concept: RTL8382M SoC 1 MIPS 4KEc core @ 500MHz 8 Internal PHYs (RTL8218B) 128MB DRAM (Nanya NT5TU128MB) 16MB NOR Flash (MXIC 25L128) 8 GBEthernet ports with one green status LED each (SoC controlled) 1 Power LED (not configurable) 1 SYS LED (configurable) 1 On-Off switch (not configurable) 1 Reset button at the right behind right air-vent (not configurable) 1 Reset button on front panel (configurable) 12V 1A barrel connector 1 serial header with populated standard pin connector and with markings GND TX RX Vcc(3.3V), connection properties: 115200 8N1 To install, upload the sysupgrade image to the OEM webpage. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
189 lines
5.9 KiB
C
189 lines
5.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _RTL838X_H
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#define _RTL838X_H
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#include <net/dsa.h>
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/*
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* Register definition
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*/
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#define RTL838X_CPU_PORT 28
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#define RTL839X_CPU_PORT 52
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#define RTL838X_MAC_PORT_CTRL(port) (0xd560 + (((port) << 7)))
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#define RTL839X_MAC_PORT_CTRL(port) (0x8004 + (((port) << 7)))
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#define RTL838X_RST_GLB_CTRL_0 (0x003c)
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#define RTL838X_MAC_FORCE_MODE_CTRL (0xa104)
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#define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc)
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#define RTL838X_DMY_REG31 (0x3b28)
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#define RTL838X_SDS_MODE_SEL (0x0028)
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#define RTL838X_SDS_CFG_REG (0x0034)
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#define RTL838X_INT_MODE_CTRL (0x005c)
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#define RTL838X_CHIP_INFO (0x00d8)
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#define RTL839X_CHIP_INFO (0x0ff4)
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#define RTL838X_SDS4_REG28 (0xef80)
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#define RTL838X_SDS4_DUMMY0 (0xef8c)
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#define RTL838X_SDS5_EXT_REG6 (0xf18c)
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#define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2))
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#define RTL839X_PORT_ISO_CTRL(port) (0x1400 + ((port) << 3))
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#define RTL8380_SDS4_FIB_REG0 (0xF800)
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#define RTL838X_STAT_PORT_STD_MIB (0x1200)
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#define RTL839X_STAT_PORT_STD_MIB (0xC000)
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#define RTL838X_STAT_RST (0x3100)
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#define RTL839X_STAT_RST (0xF504)
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#define RTL838X_STAT_PORT_RST (0x3104)
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#define RTL839X_STAT_PORT_RST (0xF508)
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#define RTL838X_STAT_CTRL (0x3108)
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#define RTL839X_STAT_CTRL (0x04cc)
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/* Registers of the internal Serdes of the 8380 */
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#define MAPLE_SDS4_REG0r RTL838X_SDS4_REG28
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#define MAPLE_SDS5_REG0r (RTL838X_SDS4_REG28 + 0x100)
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#define MAPLE_SDS4_REG3r RTL838X_SDS4_DUMMY0
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#define MAPLE_SDS5_REG3r (RTL838X_SDS4_REG28 + 0x100)
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#define MAPLE_SDS4_FIB_REG0r (RTL838X_SDS4_REG28 + 0x880)
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#define MAPLE_SDS5_FIB_REG0r (RTL838X_SDS4_REG28 + 0x980)
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/* VLAN registers */
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#define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2))
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#define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84)
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#define RTL838X_VLAN_PORT_PB_VLAN(port) (0x3C00 + ((port) << 2))
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#define RTL838X_VLAN_PORT_IGR_FLTR_0 (0x3A7C)
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#define RTL838X_VLAN_PORT_IGR_FLTR_1 (0x3A7C + 4)
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/* Table 0/1 access registers */
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#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914)
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#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2))
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#define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8)
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#define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2))
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#define RTL839X_TBL_ACCESS_CTRL_0 (0x1190)
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#define RTL839X_TBL_ACCESS_DATA_0(idx) (0x1194 + ((idx) << 2))
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#define RTL839X_TBL_ACCESS_CTRL_1 (0x6b80)
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#define RTL839X_TBL_ACCESS_DATA_1(idx) (0x6b84 + ((idx) << 2))
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/* MAC handling */
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#define RTL838X_MAC_LINK_STS (0xa188)
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#define RTL839X_MAC_LINK_STS (0x0390)
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#define RTL838X_MAC_LINK_SPD_STS(port) (0xa190 + (((port >> 4) << 2)))
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#define RTL838X_MAC_LINK_DUP_STS (0xa19c)
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#define RTL838X_MAC_TX_PAUSE_STS (0xa1a0)
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#define RTL838X_MAC_RX_PAUSE_STS (0xa1a4)
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#define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04)
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#define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08)
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/* MAC link state bits */
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#define FORCE_EN (1 << 0)
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#define FORCE_LINK_EN (1 << 1)
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#define NWAY_EN (1 << 2)
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#define DUPLX_MODE (1 << 3)
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#define TX_PAUSE_EN (1 << 6)
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#define RX_PAUSE_EN (1 << 7)
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/* EEE */
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#define RTL838X_MAC_EEE_ABLTY (0xa1a8)
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#define RTL838X_EEE_PORT_TX_EN (0x014c)
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#define RTL838X_EEE_PORT_RX_EN (0x0150)
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#define RTL838X_EEE_CLK_STOP_CTRL (0x0148)
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/* L2 functionality */
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#define RTL838X_L2_CTRL_0 (0x3200)
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#define RTL839X_L2_CTRL_0 (0x3800)
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#define RTL838X_L2_CTRL_1 (0x3204)
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#define RTL839X_L2_CTRL_1 (0x3804)
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#define RTL838X_L2_PORT_AGING_OUT (0x3358)
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#define RTL839X_L2_PORT_AGING_OUT (0x3b74)
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#define RTL838X_TBL_ACCESS_L2_CTRL (0x6900)
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#define RTL839X_TBL_ACCESS_L2_CTRL (0x1180)
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#define RTL838X_TBL_ACCESS_L2_DATA(idx) (0x6908 + ((idx) << 2))
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#define RTL838X_TBL_ACCESS_L2_DATA(idx) (0x6908 + ((idx) << 2))
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#define RTL838X_L2_TBL_FLUSH_CTRL (0x3370)
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#define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0)
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/* Port Mirroring */
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#define RTL838X_MIR_CTRL(grp) (0x5D00 + (((grp) << 2)))
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#define RTL838X_MIR_DPM_CTRL(grp) (0x5D20 + (((grp) << 2)))
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#define RTL838X_MIR_SPM_CTRL(grp) (0x5D10 + (((grp) << 2)))
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enum phy_type {
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PHY_NONE = 0,
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PHY_RTL838X_SDS = 1,
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PHY_RTL8218B_INT = 2,
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PHY_RTL8218B_EXT = 3,
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PHY_RTL8214FC = 4
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};
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struct rtl838x_port {
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bool enable;
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u64 pm;
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u16 pvid;
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bool eee_enabled;
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enum phy_type phy;
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};
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struct rtl838x_vlan_info {
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u64 untagged_ports;
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u64 tagged_ports;
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u32 vlan_conf;
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};
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struct rtl838x_switch_priv;
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struct rtl838x_reg {
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void (*mask_port_reg)(u64 clear, u64 set, int reg);
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void (*set_port_reg)(u64 set, int reg);
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u64 (*get_port_reg)(int reg);
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int stat_port_rst;
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int stat_rst;
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int (*stat_port_std_mib)(int p);
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void (*mask_port_iso_ctrl)(u64 clear, u64 set, int port);
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void (*set_port_iso_ctrl)(u64 set, int port);
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int l2_ctrl_0;
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int l2_ctrl_1;
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int l2_port_aging_out;
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int smi_poll_ctrl;
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int l2_tbl_flush_ctrl;
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void (*exec_tbl0_cmd)(u32 cmd);
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void (*exec_tbl1_cmd)(u32 cmd);
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int (*tbl_access_data_0)(int i);
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int isr_glb_src;
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int isr_port_link_sts_chg;
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int imr_port_link_sts_chg;
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int imr_glb;
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void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info);
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void (*vlan_set_tagged)(u32 vlan, u64 portmask, u32 conf);
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void (*vlan_set_untagged)(u32 vlan, u64 portmask);
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int (*mac_force_mode_ctrl)(int port);
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int rst_glb_ctrl;
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};
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struct rtl838x_switch_priv {
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/* Switch operation */
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struct dsa_switch *ds;
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struct device *dev;
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u16 id;
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u16 family_id;
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char version;
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struct rtl838x_port ports[54]; /* TODO: correct size! */
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struct mutex reg_mutex;
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int link_state_irq;
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int mirror_group_ports[4];
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struct mii_bus *mii_bus;
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const struct rtl838x_reg *r;
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u8 cpu_port;
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u8 port_mask;
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};
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extern struct rtl838x_soc_info soc_info;
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extern void rtl8380_sds_rst(int mac);
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extern int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
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extern int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
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extern int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
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extern int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
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extern int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val);
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extern int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val);
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#endif /* _RTL838X_H */
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