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3c69b9a818
This is an automatically generated commit. When doing `git bisect`, consider `git bisect --skip`. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
139 lines
3.2 KiB
Diff
139 lines
3.2 KiB
Diff
From f4318af40544b8e7ff5a6b667ede60e6cf808262 Mon Sep 17 00:00:00 2001
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From: Martin Botka <martin.botka@somainline.org>
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Date: Mon, 19 Feb 2024 15:36:39 +0000
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Subject: [PATCH] arm64: dts: allwinner: h616: Add thermal sensor and zones
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There are four thermal sensors:
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- CPU
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- GPU
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- VE
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- DRAM
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Add the thermal sensor configuration and the thermal zones.
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Signed-off-by: Martin Botka <martin.botka@somainline.org>
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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Link: https://lore.kernel.org/r/20240219153639.179814-8-andre.przywara@arm.com
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Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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---
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.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 88 +++++++++++++++++++
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1 file changed, 88 insertions(+)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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@@ -9,6 +9,7 @@
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#include <dt-bindings/clock/sun6i-rtc.h>
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#include <dt-bindings/reset/sun50i-h616-ccu.h>
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#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
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+#include <dt-bindings/thermal/thermal.h>
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/ {
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interrupt-parent = <&gic>;
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@@ -138,6 +139,10 @@
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reg = <0x03006000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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+
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+ ths_calibration: thermal-sensor-calibration@14 {
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+ reg = <0x14 0x8>;
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+ };
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};
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watchdog: watchdog@30090a0 {
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@@ -511,6 +516,19 @@
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};
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};
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+ ths: thermal-sensor@5070400 {
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+ compatible = "allwinner,sun50i-h616-ths";
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+ reg = <0x05070400 0x400>;
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+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_THS>;
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+ clock-names = "bus";
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+ resets = <&ccu RST_BUS_THS>;
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+ nvmem-cells = <&ths_calibration>;
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+ nvmem-cell-names = "calibration";
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+ allwinner,sram = <&syscon>;
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+ #thermal-sensor-cells = <1>;
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+ };
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+
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usbotg: usb@5100000 {
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compatible = "allwinner,sun50i-h616-musb",
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"allwinner,sun8i-h3-musb";
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@@ -755,4 +773,74 @@
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#size-cells = <0>;
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};
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};
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+
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+ thermal-zones {
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+ cpu-thermal {
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+ polling-delay-passive = <500>;
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+ polling-delay = <1000>;
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+ thermal-sensors = <&ths 2>;
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+ sustainable-power = <1000>;
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+
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+ trips {
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+ cpu_threshold: cpu-trip-0 {
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+ temperature = <60000>;
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+ type = "passive";
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+ hysteresis = <0>;
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+ };
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+ cpu_target: cpu-trip-1 {
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+ temperature = <70000>;
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+ type = "passive";
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+ hysteresis = <0>;
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+ };
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+ cpu_critical: cpu-trip-2 {
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+ temperature = <110000>;
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+ type = "critical";
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+ hysteresis = <0>;
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+ };
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+ };
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+ };
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+
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+ gpu-thermal {
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+ polling-delay-passive = <500>;
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+ polling-delay = <1000>;
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+ thermal-sensors = <&ths 0>;
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+ sustainable-power = <1100>;
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+
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+ trips {
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+ gpu_temp_critical: gpu-trip-0 {
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+ temperature = <110000>;
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+ type = "critical";
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+ hysteresis = <0>;
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+ };
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+ };
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+ };
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+
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+ ve-thermal {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&ths 1>;
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+
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+ trips {
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+ ve_temp_critical: ve-trip-0 {
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+ temperature = <110000>;
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+ type = "critical";
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+ hysteresis = <0>;
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+ };
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+ };
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+ };
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+
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+ ddr-thermal {
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&ths 3>;
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+
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+ trips {
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+ ddr_temp_critical: ddr-trip-0 {
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+ temperature = <110000>;
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+ type = "critical";
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+ hysteresis = <0>;
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+ };
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+ };
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+ };
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+ };
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};
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