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Patch generation process: - rebase rpi/rpi-4.14.y on v4.14.89 from linux-stable - git format-patch v4.14.89 Patches skipped during rebase: - lan78xx: Read MAC address from DT if present - lan78xx: Enable LEDs and auto-negotiation - Revert "softirq: Let ksoftirqd do its job" - sc16is7xx: Fix for multi-channel stall - lan78xx: Ignore DT MAC address if already valid - lan78xx: Simple patch to prevent some crashes - tcp_write_queue_purge clears all the SKBs in the write queue - Revert "lan78xx: Simple patch to prevent some crashes" - lan78xx: Connect phy early - Arm: mm: ftrace: Only set text back to ro after kernel has been marked ro - Revert "Revert "softirq: Let ksoftirqd do its job"" - ASoC: cs4265: SOC_SINGLE register value error fix - Revert "ASoC: cs4265: SOC_SINGLE register value error fix" - Revert "net: pskb_trim_rcsum() and CHECKSUM_COMPLETE are friends" - Revert "Revert "net: pskb_trim_rcsum() and CHECKSUM_COMPLETE are friends"" Patches dropped after rebase: - net: Add non-mainline source for rtl8192cu wlan - net: Fix rtl8192cu build errors on other platforms - brcm: adds support for BCM43341 wifi - brcmfmac: Mute expected startup 'errors' - ARM64: Fix build break for RTL8187/RTL8192CU wifi - ARM64: Enable RTL8187/RTL8192CU wifi in build config - This is the driver for Sony CXD2880 DVB-T2/T tuner + demodulator - brcmfmac: add CLM download support - brcmfmac: request_firmware_direct is quieter - Sets the BCDC priority to constant 0 - brcmfmac: Disable ARP offloading when promiscuous - brcmfmac: Avoid possible out-of-bounds read - brcmfmac: Delete redundant length check - net: rtl8192cu: Normalize indentation - net: rtl8192cu: Fix implicit fallthrough warnings - Revert "Sets the BCDC priority to constant 0" - media: cxd2880: Bump to match 4.18.y version - media: cxd2880-spi: Bump to match 4.18.y version - Revert "mm: alloc_contig: re-allow CMA to compact FS pages" - Revert "Revert "mm: alloc_contig: re-allow CMA to compact FS pages"" - cxd2880: CXD2880_SPI_DRV should select DVB_CXD2880 with MEDIA_SUBDRV_AUTOSELECT - 950-0421-HID-hid-bigbenff-driver-for-BigBen-Interactive-PS3OF.patch - 950-0453-Add-hid-bigbenff-to-list-of-have_special_driver-for-.patch Make I2C built-in instead of modular as in upstream defconfig; also the easiest way to get MFD_ARIZONA enabled, which is required by kmod-sound-soc-rpi-cirrus. Add missing compatible strings from 4.9/960-add-rasbperrypi-compatible.patch, using upstream names for compute modules. Add extra patch to enable the LEDs on lan78xx. Compile-tested: bcm2708, bcm2709, bcm2710 (with CONFIG_ALL_KMODS=y) Runtime-tested: bcm2708, bcm2710 Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
47 lines
1.8 KiB
Diff
47 lines
1.8 KiB
Diff
From ae5d39403c61f4ed691a0a8d94673210475242be Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Tue, 15 Aug 2017 16:47:18 -0700
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Subject: [PATCH 204/454] drm/vc4: Move the DSI clock divider workaround closer
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to the clock call.
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We want the adjusted_mode->clock to be the actual clock we're
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expecting to program, so that consumers see the right values for clock
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and vrefresh.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Link: https://patchwork.freedesktop.org/patch/msgid/20170815234722.20700-1-eric@anholt.net
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Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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(cherry picked from commit d409eeafa9ba1c0f2eb75a2619fc787808a545e4)
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---
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drivers/gpu/drm/vc4/vc4_dsi.c | 12 ++++++------
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1 file changed, 6 insertions(+), 6 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_dsi.c
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+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
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@@ -864,11 +864,7 @@ static bool vc4_dsi_encoder_mode_fixup(s
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pll_clock = parent_rate / divider;
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pixel_clock_hz = pll_clock / dsi->divider;
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- /* Round up the clk_set_rate() request slightly, since
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- * PLLD_DSI1 is an integer divider and its rate selection will
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- * never round up.
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- */
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- adjusted_mode->clock = pixel_clock_hz / 1000 + 1;
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+ adjusted_mode->clock = pixel_clock_hz / 1000;
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/* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
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adjusted_mode->htotal = adjusted_mode->clock * mode->htotal /
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@@ -906,7 +902,11 @@ static void vc4_dsi_encoder_enable(struc
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vc4_dsi_dump_regs(dsi);
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}
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- phy_clock = pixel_clock_hz * dsi->divider;
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+ /* Round up the clk_set_rate() request slightly, since
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+ * PLLD_DSI1 is an integer divider and its rate selection will
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+ * never round up.
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+ */
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+ phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
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ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
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if (ret) {
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dev_err(&dsi->pdev->dev,
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